Re: Multi-phase detector in CDR circuit; Not half rate or fu
Dear sutapanaki
Thank you indeed. I 'd like to explain my system clear.
I have to build a 1GHz data rate SerDes in one chip. And I have a 100Mhz+/-100ppm local reference x'tal clock on this chip. Obviously, the 10:1 ratio is due to 8B/10B encoder on chip for DC balance.
TX structure.
8 bit @ 100MHz ==> 8B/10B Encoder ==> 10 bit @ 100MHz ==> Serializer ==> 1 Bit @1GHz
I will use a PLL to generte the evenly spaced 10 phases of 100MHz clock which will serve the clock source for the serializer.
RX structure,
RX is receiving the 8B/10B coded data stream from another similar SerDes chip with embeded clock and slightly different frequency , say, 100MHz+/- 200ppm.
Since the local clock 100MHz+/-100ppm is different from in coming embeded clock, I will have to use a CDR to recover the clock from data with embeded clock.
1 bit @ 1GHz+/- 200ppm ==> CDR ==> 10 bit@ 100 Mhz +/- 200ppm PLUS 10 phases 100MHz +/- 200ppm
That's why I hope to have a sub-rate multi phase detector, say, 5 or 10 phase detector for the CDR.
If we use the quad-rate phase detector for CDR( there is a lot of from Razavi's students dealling with that) , I need to modify the SerDes entirely, especially at clock domain.
NEW TX structure
8 bit @ 100MHz ==> 8B/10B Encoder ==> 10 bit @ 100MHz ==> 10B/8B converter ==> 8 bit @ 125MHz==> Serializer ==> 1 Bit @1GHz
So will have to generate the 8 phases 125MHz from local reference clock.
NEW RX structure
1 bit @ 1GHz+/- 200ppm ==> CDR ==> 8 bit@ 125 Mhz +/- 200ppm PLUS 8 phases 125MHz +/- 200ppm ==> 8B/10B converter==> 10 bit@ 100 Mhz +/- 200ppm PLUS 1 phase 100MHz +/- 200ppm from addtional PLL.
It seems more work to me comparing with the previous structure, that 's why I am seeking the 5 or 10 phase sub-rate phase detector.
One more question, how about the frequency locking range of normal CDR phase detector, say 1%? Or less than 1 %?
Please advise,
Thanks in deed!
Raymond