[SOLVED] Multi cycle path in STA

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c_ssood

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Take the case of a multi cycle path. If the specification is 2 cycles for the setup time, why one always specifies the hold cycle time to be 1 cycle?
 

think of a regular path without MC. setup is 1 clock cycle (edge to next clock edge), hold is 0 clock cycles (same clock edge).

when you make a MC path of 2, setup is 2, but hold doesn't have to be 0. it can be 1.
 

When setup check is moved using MC path of 2, the STA tool also move the hold check up, which is not desirable as it is over constraining the design. Hold is 0 clock cycle ( same clock edge) , so hold check up is moved back to same clock edge by specifying in MC constrain.
 

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