atran_zh
Newbie level 2
multi-bits sigma-delta
Hello everybody
Nice to join this forums. Does anybody has experience with Verilog HDL code for Delta-Sigma DAC. I have simulated the delta-sigma loop multi-bits for WLAN with Matlab
OSR = 4( Oversampling Ratio)
BW = 10 MHz ( Bandwidth)
The matlab simulation shows that the achieved SQNR for the case of MASH 4th order with 5 bits quantizer is 73 dB, whereas the required SQNR is 68 dB.
Now i must write the Verilog code for this Matlab block. I began with the first order, second order in Verilog HDL, but I see the simulation is totally different with the one from Matlab, the NOISE is NO SHAPED with the Verilog Code. And I am now looking to fix the errors, but it is very difficult, because I have very little exprience with digital-design.
Can anybody help me, or give some advices? Has anybody here the Verilog code just for 2nd order delta-sigma loop ??
Added after 1 minutes:
If you are interested, I can upload my simulation result with Matlab to the forum.
Hello everybody
Nice to join this forums. Does anybody has experience with Verilog HDL code for Delta-Sigma DAC. I have simulated the delta-sigma loop multi-bits for WLAN with Matlab
OSR = 4( Oversampling Ratio)
BW = 10 MHz ( Bandwidth)
The matlab simulation shows that the achieved SQNR for the case of MASH 4th order with 5 bits quantizer is 73 dB, whereas the required SQNR is 68 dB.
Now i must write the Verilog code for this Matlab block. I began with the first order, second order in Verilog HDL, but I see the simulation is totally different with the one from Matlab, the NOISE is NO SHAPED with the Verilog Code. And I am now looking to fix the errors, but it is very difficult, because I have very little exprience with digital-design.
Can anybody help me, or give some advices? Has anybody here the Verilog code just for 2nd order delta-sigma loop ??
Added after 1 minutes:
If you are interested, I can upload my simulation result with Matlab to the forum.