It depends on the spec of the SD ADC as well as it's architecture - there's no general answer if internal ADC will dominate power consumption.
But in my experience, the internal quantizer is not the major contributor to overall power consumption. Usually OTAs in the loop filter (especially in the first integrator) consume more current.
Usually the requirements to the linearity of the internal ADC in the quantizer are not very strict, because it is in the loop, so it's error is noise-shaped. Low hysteresis is a more important then offset.
However the linearity of the feedback is VERY important, so usually special techniques are used to improve it.