Why not use an Altera MAXII CPLD, this would give a one chip solution with plenty of space, the only problem is that it is not 5v tolerant.
These are easy to replace with ordinary SRAMs like 2Kx8, 8Kx8 or 32Kx8. 5V versions of those are still available brand new.because it has a few of the tiny 64-bit RAM chips, and two of the other cards (to be done later) have the 2114 1,024 x 4 bit static RAM chips (which themselves are the primary reason these 30+ year old cards are failing).
Unlikely since the logic inside is a 'black box', maybe chip-level software emulation exists for systems that use this IC but that's not good enough to re-implement the chip itself.Can the TMS2793 be somehow replaced with programmable logic?
You'd have to talk to TI (and/or Western Digital) about that, I assume they have records of what logic is in the TMS2793. But unless you'd want to mass-produce something incorporating a 2793, I doubt that would bring anything.I'd assume that it is such old junk that no one bothered to make it a licensable core IP.
Yes, and with a mixup of 74xx, 74ASxx, 74Sxx and 74ALSxx parts - wouldn't surprise if there's some race conditions in that logic which happen to work correctly with the parts that are fitted. Must be eating a significant amount of power too. Anyway, doesn't seem like a particular difficult or complicated project (just time-consuming)... Without interesting IC's, this system would be something like a discrete logic CPU? Or just logic, processing I/O signals (where the 'smarts' is in the logic itself). :?:One important thing about the conversion is the usage of asynchronous or synchronous memories.
The original RAMs and ROMs can probably be used asyncronously, but some embedded memories in programmable logic must be used synchronously.
This probably prevents a "stupid" conversion by just entering the reversed-engineered schematic.
If you understand what's going on, the conversion should be straightforward.
Actually most of those things aren't unreasonable: copying circuit boards is an option, and most of these 74xx series IC's are still sold, brand new if you want (or newer alternatives like 74HCT, 74ACT families etc). And while ancient, plain 74xx logic is generally quite robust / reliable. If speed of the system is low, a sufficiently fast clocked microcontroller might just be able to do in software, what plain logic does in hardware (and software development for PIC, AVR & co possibly easier than CPLD / FPGA logic design). Also developing programmable logic using out-of-production parts + 'ancient' software versions, is not uncommon. Not everyone likes to use the newest parts + software all the time, and there's rarely a pressing need to do so.The #3 "engineers/companies overseas" have real language problems, and often claim to be able to do anything under the sun, so long as "anything under the sun" is taking an existing card, desoldering the chips, scanning the bare PCB onto film, then making exact PCBA copies of the cards. They can't possibly grasp what I am saying, and think it is totally reasonable to mass produce cards that are chock full of DIP parts that haven't been made since Reagan was President, and using programmable devices for which programming services/programming hardware hasn't existed for decades. Most of the few that actually want to put some engineering into it quickly say that the way to do it is with a microcontroller like a PIC or Atmel, proving they don't even barely understand how a dumb logic board sits on a CPU bus.
That is too bad, as it would require you to do all real-hardware testing, which in turn could very much lengthen the design change <-> test cycle time. Also I can understand the need to keep a business secret, but a written contract including non-disclosure clause (with appropriate penalties if violated) could fix that. Btw as a practical matter: do you have blank boards to copy PCB track layout? That would be very helpful in re-producing a schematic. If only populated boards are available, I'd need physical item in hand since you can't trace connections that go underneath components from a photograph.The original system is not going to be available to someone working on the project unless a seriously complicated problem requires it.
No offense, but that's just stupid. Timing is a very important aspect of any logic circuit, and this may (ehm... will) depend on actual parts fitted (+their propagation delay), the number of logic gates a signal goes through, whether its clocked asynchronously or synchronously, or even how many inputs an output is driving. Basically "copy schematic into CPLD design software" will not do it, I can assure you. Hence my "determine what logic does, come up with CPLD / FPGA equivalent that does the same" approach.(..) if you can't move a dumb logic board of forty 7400 series chips to programmable logic just by duplicating the schematic, you don't understand logic or programmable logic.
What I suspect you mean is: "reponds in the same way (and @ same time) to external 'stimuli' as original". That leave open plenty of optimization options. Just 1 example: suppose you have a memory block consisting of 8 IC's + a 3-to-8 decoder for /CS signals. Sure you could duplicate that, but: higher-level view is it's a single memory block the size of those 8 IC's combined. No need for decoder or 8 separate memory blocks. There are countless examples like this (and programmable logic is very flexible in this regard).I should also note that this logic needs to be put into a programmable device verbatim, without any optimizing of routines or "improvements". This system has peripheral functions which may depend on any quirks that existed in the original, and making an emulation of it or making it "better" defeats the purpose of the project.
Makes perfect sense. Since I'm assuming boards are not connected A -> B -> C -> D fashion, but rather each board with edge connector to (some sort) of common bus, this would also mean that a card which can interface to that bus, in theory can perform the function of X number of boards connected to that bus.When we use a 3.3v chip for this instead of the 5v I/O chip that I want to use, I am the one who is going to have to make what could have been a single chip board into a board chock full of regulators and level shifters, then I will have to make a board chock full of regulators and level shifters, then I will have to make a board chock full of regulators and level shifters, (..)
Doing that 17 times? Not. If that makes sense to you, it only makes sense because you're not the one building stupid hardware 17 times for no reason other than not having used the right chip in the first place.
Doesn't compute: this would require selection of individual chips (in a JTAG chain), and maintaining individual programming files for these chips. If you change function of 3 of those, 3 chips to re-configure. And complicated circuit board with lots of wiring between chips. In contrast if you integrate into smallest number of CPLD / FPGA, then ideally whatever change you make, only 1 chip to re-configure. And board layout as simple as can be / lowest possible per-unit cost. Of course one would like a modular approach, but there's more ways than 1 to get that.Though I hope to get the whole thing down to a pair of programmable logic chips, the more I think about it, the more I think it will make sense to have 17 chips on a motherboard. It will just make it a lot easier to get around and modify, etc..
Good to hear, I read that simply as a reduction in requirements (fewer/smaller RAM blocks needed).I misspoke previously when I said the boards would probably need to have some ROM and RAM chips. That isn't correct, and for a lot of obvious reasons, it would be best not to use any external RAMs or ROMs.
Not in the case of CPLD's (at least all Xilinx ones that I know) - basically these have 1 bit of memory per macrocell, and largest CPLD's (in BGA housing!) have a few hundreds of those. Perfectly adequate for implementing state machines, counters, a small block of registers etc. But as soon as any significant size memory block (>a few dozen bits) is introduced, you're looking at a FPGA. If a memory block can be included in the FPGA, you save I/O pins that you would otherwise need to connect external ROM/RAM.A discussion with an engineer last week reminded me that the function of RAM can be duplicated in programmable logic. It tends to burn the resources of the chips off on a fairly pedestrian function that a lot of people would prefer to do off-chip, but those resources are cheap now.
XC9500XL isn't a part, but a family of devices. And judging by some stories on Xilinx forums, possibly not as 5V tolerant as you'd like. So it might even make sense to use devices from XC9500 family. Personally I think 3.3V <-> 5V interfacing is much easier to deal with than 5V parts becoming obsolete/hard-to-find/expensive. If chosen parts are 5V tolerant, that just makes things easier but it isn't very important.The Xilinx XC9500XL seems to make the most sense for a lot of reasons (it's a $1 part, it's 5v tolerant, and it isn't 100,000 times what I need---as anything else is).
Thx! :-D Currently working on a Sinclair **broken link removed** (about 15-20 74xx IC's worth), this is mostly done by now.RetroTechie, thanks for the reply. I love your website! Your experience is very, very close to what this is.
To be honest I haven't got a clue about how to put a price tag on a job like this (especially since it isn't clear yet exactly how big a job it is, or what's required for successful completion). I don't think this is a small job, but if your budget is reasonable, I'm sure we could work something out... :-DPlease review my updates that clear up a lot of what I left out of the OP, and send me a PM with a price estimate if you think you can do one of these cards, and ask me any specific questions I might have left out.
Some recent threads on Xilinx user forum that might be of interest:If you can point me to any Xilinx forum posts that outline problems with 5v I/O tolerance not being as claimed by Xilinx, I'd appreciate it.
Like I said: timing is a very important aspect of digital circuitry, and there's many factors that have an influence on that (temperature, logic families, wire lengths(!), input capacities, etc, etc). A schematic says a lot, but only shows part of the picture. Any (competent) digital designer will know that ultimately, all logic circuits are analog too. Newbies / students might have difficulties grasping that, experienced designers might sometimes forget it, but that analog aspect never goes away. At best, for practical purposes you can ignore it (given a set of operating conditions).You've said "Basically "copy schematic into CPLD design software" will not do it, I can assure you." That is a very interesting and provocative thought that, if correct, nearly kills my project. Logic chips on a board have a function that the same logic in a CPLD/PGA does not? Makes me wonder how anyone designs logic now, if the programmable logic can't perform the same functions as the old logic in the same way.
There you go - see what I mean? :wink:Some things don't seem to be slot-dependent, but some cards that are all the same in equal slots like 6 7 8 9 (some with DIP switches to address the cards, some without) can NOT be put in like 6 8 9 7. Although it would seem that they are all connected together purely in parallel, no, they have to be in an order. I don't know if it is bus timing or what, but I am aware of it. Also, various revisions of various boards and backplanes have a mess of pullup/pulldown resistors soldered in place on the PCB and piggybacked over chips that presumably didn't work right without it, plus caps and whatever.
Yes that's the essence, this Wikipedia article is a better start. The pictures in it showing 2 NOR gates or 2 NAND gates basically show a single bit of memory (like what you'd find 4096 of in that 'antique' 2114 static RAM).Not sure if I sufficiently explained the matter of doing the RAM in the CPLD without using an external RAM. I'd given this link:
Logic gate - Wikipedia, the free encyclopedia
I don't know anything about logic, but I thought the idea there was to set a gate to a state, latch it, then when you want, go back and read that state, thus creating a form of RAM.
One more note, the engineer who is doing the first card (not shown here) which has a lot of 2114 RAMs on it had said he was definitely going to do the RAM outside the CPLD/PGA. Not sure if he was consolidating it all to one chip or not, but probably so.
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