[Moved] Verilog Question about instantiating

Code Verilog - [expand]
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// this a sample program to help u learn how to tie the variables
// hope if u understand the module u ll realise...
/// also try simulating them
 
module mod1 (en, clk, count,rst);
input en,rst;
input clk;
output reg [3:0] count ;
 
always@(posedge clk) 
begin
      if (en==1'b0) begin
         count<=4'b0000;
      end else if (en ==1'b1) begin
         count<=count+4'b0001;
    end else if (rst) begin
         count<=4'b0000;
    end      
        
end
endmodule
 
module mod1_tb ();
    reg tb_en, tb_clk, tb_rst;
    wire [3:0] tb_count;
    
mod1 mod1_tb(.en(tb_en),.rst(tb_rst),.clk(tb_clk),.count(tb_count));
 
initial
begin
 
tb_en=0;
tb_rst=0;
tb_clk=0;
 
#50 tb_rst=1;
#50 tb_rst=0;
#50 tb_en=1;
#1800 tb_en=0;
   
#2000 $finish;
end
 
always
begin
#50 tb_clk=~tb_clk;
end
endmodule