[Moved] Verilog : can "initial" be used in main module?

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jesslyn993

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I wish to have my codding executing in sequential way. But I read from internet, all verilog code was as default run in concurrent way unless i make it in initial or always block and using blocking assignment.

Thus, I modify my code by using initial block to cover all my coding in main module.

FYI: I have a C coding from arduino to run my NFC reader. I wanted it to be in verilog coding. Thus, I write the verilog coding according to the C coding. Since C coding execution is in sequential way, thus i wanted my verilog to execute in sequential way.


Question:
Is it okay to use initial to include all my coding in main module?



Please give me a hand. Thanks
 

Your question leads me to believe the support for "initial" and "always " is not what you intend to use it for.

including all logic in initial is something that would not make sense. It is almost certainly a misunderstanding of how that construct was intended to be used.
 

I guess, you are misunderstanding the meaning of sequential logic blocks in hardware description languages like Verilog or VHDL. They imply a sequential elaboration but not a sequential execution in time as you can expect it with microcontroller C code.

It's not possible to simply translate C to Verilog. You need to understand the different nature of programmable logic and microcontroller code and design logic hardware that performs the intended sequential action, e.g. a finite state machine.
 

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