Shady Ahmed
Member level 5
Hello,
I am trying to write verilog-A code to model a circuit that acts as an analog timer.
By default, the output is High, when it receives start signal (positive edge), the output should be low for a constant time (say 10u seconds) then it goes HIGH again.
Here is the code, however it doesn't seem to work.
Any help?
I am trying to write verilog-A code to model a circuit that acts as an analog timer.
By default, the output is High, when it receives start signal (positive edge), the output should be low for a constant time (say 10u seconds) then it goes HIGH again.
Here is the code, however it doesn't seem to work.
Any help?
Code:
// VerilogA for ELC612, Analog_Timer, veriloga
`include "constants.vams"
`include "disciplines.vams"
module Analog_Timer(start,Vout);
input start;
output Vout;
electrical start, Vout;
parameter real ton=1u;
parameter real Vmax=1.5;
parameter real vtrans_clk=1.65;
parameter real vlogic_high=3.3;
parameter real vlogic_low = 0;
parameter trise=200e-9;
parameter tfall=200e-9;
parameter real tdel = 0;
integer next,temp;
analog begin
@ (cross( V(start) - vtrans_clk, +1,1n )) begin
next = $abstime ;
temp= 0;
end
@ (timer(next))
temp= 1;
V(Vout) <+ transition( temp? vlogic_high: vlogic_low,
tdel, trise, tfall );
end
endmodule