[Moved] [STA] FPGA ROUTING block representation for top-level STA

[amphibionics]

[STA] FPGA ROUTING block representation for top-level STA

Hi, anybody here doing IP characterization for FPGA? I just wonder how do you represent ROUTING block for top-level STA.

I am doing top-level STA using FPGA IPs but to correctly represent the actual FPGA setup, I need not just IP block timing models but also ROUTING.
Basically, I have two problems here:
1. How can I represent ROUTING block for top-level in FPGA?
2. How can I capture the delays due to the wire loads?

By the way, I am using PrimeTime for top-level STA.
Thanks.

 

[ads-ee]

Routing for an FPGA isn't the same as for an ASIC. There are all kinds of switch matrices (transistors) that are part of the routing. Besides the routing can change from build to build, so you would be hard pressed to characterize the IP's routing.

If you a talking about designing and characterizing an embedded hard IP block. Then the post being moved from what I assume was the ASIC Design Methodologies... portion of the forum was a mistake. I would assume in that case the hard IP is characterized just like any other ASIC IP block. Basically after the layout is complete and all the metal layers have been defined and the extraction has been done.

 

[amphibionics]

Thanks ads-ee. :grin:
Yes, you've correctly pointed-out the real problem with characterizing routing IPs in the first part of your reply and that's where I'm looking for help.

And also yes, this was originally posted in ASIC Design Methodologies forum but was moved by admin. You're correct that characterizing FPGA hard IPs is just the same with ASIC. It's just that all IP configurations should be taken into account and routing I think is the hardest part.

 

[ads-ee]

I don't think there is an actual solution to characterizing the routing as FPGA routing can vary wildly from run to run especially when the design is heavily utilized. I've even seen designs not meet timing when the design has less than 20% utilization due to the placement algorithm doing a bad job of locating the critical path logic next to each other.

Good luck on your attempt to "characterize" soft IP routing. Honestly I think you're wasting your time.

Regards

 

[amphibionics]

Yeah right, well said.
That's why before wasting too much time and effort, I looked for consultation in this site.
Actually, I am involved in FPGA design in the HW IP level not on the board level.
Currently, we don't have methodology yet for Full-chip timing analysis.
And I think based on your suggestions, you're saying that doing Full-chip timing analysis is by using only HW IPs with no routing IP block in between and just consider 1 particular scenario in the timing analysis.
Would this suffice in determining the critical path of the design before tape out?

Thanks.