Tarunfpga1
Newbie level 4
There is a VHDL code which i synthesized for Xilinx Virtex-5 FPGA device. Now that is very small code which has 4-bit input and 4-bit output and it is purely combinational, no clk is used.
After synthesis i am getting the results which are as follows:
no. of LUTs - 4 which is understandable but no. of slices are used equal to 3.
Now, my question is that in virtex-5 a slice has 4 LUTs so if total 4 LUTs are utilizing then there should be only 1 slice but why it is showing 3 slices ??
After synthesis i am getting the results which are as follows:
no. of LUTs - 4 which is understandable but no. of slices are used equal to 3.
Now, my question is that in virtex-5 a slice has 4 LUTs so if total 4 LUTs are utilizing then there should be only 1 slice but why it is showing 3 slices ??