[moved] sar adc comparator design

[rajua]

im designing double tail comparator for sar adc. Im getting clock signal when input voltage is above reference voltage. How to get low voltage when vin is below reference voltage. Why clock signal is getting triggered in the output signal instead of zero volts. Please reply me..

 

[dick_freebird]

Some questions here before like this, have been because
the "comparator" that shows up in easy searching is only
part of the real comparator block - the decision front end,
but requiring a latch after it or crazy "output" (which is
not the real, desired output) behavior (relative to what
a true complete comparator would be expected to do)
is seen and confuses people.

With no schematic, no waveforms that's about all I can
(or care to) speculate.

 

[rajua]

is that a correct output?

 

[Dominik Przyborowski]

I don't know what is represented by out signal but von and vop showing correct behaviour for dynamic comparator.