quyleanh
Member level 3
I have question about processing of Native MOS Transistor. Thank you for answering me.
As I know, Native MOS is N type MOS which is formed directly to substrate. In my working technology, there is layer call Native which cover all the area of Nselect layer (and of couse, Nisland as well).
My question is, if we see in 3D silicon structure, which will the Native be, and how will it form?
I try to draw the structure as picture below.
My understanding is there will be a light N type implant under Gate region which is doped to substrate to make the Threshold voltage small, or even negative (because the 2 N+ implant channel are already connected together with this above light N type implant).
Correct me if I am wrong. Thank you very much.
As I know, Native MOS is N type MOS which is formed directly to substrate. In my working technology, there is layer call Native which cover all the area of Nselect layer (and of couse, Nisland as well).
My question is, if we see in 3D silicon structure, which will the Native be, and how will it form?
I try to draw the structure as picture below.
My understanding is there will be a light N type implant under Gate region which is doped to substrate to make the Threshold voltage small, or even negative (because the 2 N+ implant channel are already connected together with this above light N type implant).
Correct me if I am wrong. Thank you very much.