Re: PNP in CMOS different sizes
The differences are obviously emitter area and periphery.
Area goes to the current density where peak hFE is found.
For low power you generally want smaller, to get best OP
hFE.
But small devices also have a larger periphery to area ratio
and some hFE degradation relates more to periphery than
areal current density - current injected laterally crosses a
wider (lower or no gain) base, tends to be recombined at
a substantial loss.
Larger features tend to match better / more consistently.
Meaning perhaps less scatter in your untrimmed bandgap
voltage & tempco.
You could see what the models show when put into classic
characterization testbenches (hFE vs Ic, w/ Vce - although
often the PNP is a diode connected substrate PNP used only
for bandgaps, in which case Vce=Vbe and you can cut down
on that dimension; Gummel plot, which can show you some
stuff about where and where is not, the log-Ic vs Vbe linear.
Then you would like to repeat this on a probe station or on
packaged units (perhaps arrays, since one is tiny) and see
just how much your foundry cared about accuracy on a
"freebie" (zero effort -> low expectations) transistor.