Increase V4 voltage at least 160mV, decrease V2 voltage at least 500mV. Use bigger W/L for top PMOS devices, first double them for example. Those have too high Vdsat.
I wouldn't decrease NMOS W/L. But increase PMOS, 4 times maybe. You should go below 200mV Vdsat for all devices. That is normal.
Next time please annotate the node voltages too. I didn't see your circuit is toggled. Without feedback or control voltage you can't ensure to keep the transistors in saturation, because your circuit has got an asymmetric second stage and possibly a hugh gain. It is totally normal that the output voltage is almost equals with the supply rail's voltage then.
Connect NM0's gate to the output and connect NM3's gate to 0.6V. It creates negative feedback, and you can test your circuit with a normal bias condition and set the 2nd stage's transistors.
I don't understand why you cannot implement the feedback for only one stage. To set the proper bias for one stage you should try that. If you set it should be good for more stages.
I don't know the DC values of Vi1, Vi2 and Vi3. Without these I cannot say a good solution. What are the DC values of these sources?
How much are the Gm1, Gm2, Gm3? Also can be important, and a side question, why do you need 3 inputs?
No. I said set the operating points separately. When the stages are not connected together, connect NM0's gate to the output and connect NM3's gate to 0.6V. Set Gm and Vdsat.
After you finished connect the stages together by your figure and connect Vi1 and Vi3 to 0.6V common mode voltage.
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