[Moved]: Monte Carlo Yield Analysis

[analogengineerrf]

Hello All,

Please tell me how to decrease the mismatch and increase the yield of my designed Operational Amplifier, as during the monte carlo simulation for yield analysis, the open loop gain drops too large from the gain value it has been designed for. Any help would be highly appreciated.

Thanks in advance.

 

[Dominik Przyborowski]

Re: Monte Carlo Yield Analysis

If You are using a few replicas to simulate open loop gain, the bad results of MC sims are normal ;-)

 

[crutschow]

Re: Monte Carlo Yield Analysis

You have to determine what part is affecting the gain adversely and try to tighten it's parameters, or alter the circuit so that part doesn't have such a large effect on the gain.

 

[BigBoss]

Re: Monte Carlo Yield Analysis

Hello All,

Please tell me how to decrease the mismatch and increase the yield of my designed Operational Amplifier, as during the monte carlo simulation for yield analysis, the open loop gain drops too large from the gain value it has been designed for. Any help would be highly appreciated.

Thanks in advance.

Check the "Sensitivity" of your circuit against components' tolerances by doing "Peroto Analysis" then work on those components to improve the performance.If you work on Cadence ADE (G)XL, you'll find how to do this Peroto Analysis ( or Sensitivity Analysis )

 

[dick_freebird]

Re: Monte Carlo Yield Analysis

Begin with separating the mismatch and deterministic (process)
effects. Look to your testbench, which if DC open loop will be
very mismatch (Vio) sensitive. The only thing that (in simulation)
will decrease mismatch is device area. Some matter more than
others. There is a price to be paid for using more area (BW, Icc)
of course, so you want to be sure you're getting your "money's
worth" on anything you upsize.

 

[analogengineerrf]

Re: Monte Carlo Yield Analysis

Thanks to all for the kind help.

To give an idea about my design, I am using the Beta Multiplier Reference circuit to generate a reference current of 10uA. The circuit has a resistor in the drain side. How much may be the effect of this resistor in Monte Carlo mismatch analysis simulation?

The gain according to my requirement is 80db with Typical PMOS and NMOS models and at 25 degrees temperature with 1.8 V Supply.

The Gain analysis with varying Processes is also under acceptable limits, but while doing Monte Carlo Simulation, the Gain drops to 20dB and is centered around it only for 1000 runs. Only a single sample out of 1000 runs shows 80dB gain.

and I am using Synopsys Galaxy Schematic designer and HSPICE in SAE (Simulation and Analysis Window) for my design.

Please help me with some idea. Thanks in advance.

 

[dick_freebird]

Re: Monte Carlo Yield Analysis

See what you can do about asserting a particular MC seed
& iteration, to get at a problem case deterministically. We
used to have this ability "back in the day" but this was with
a particular foundry's legacy process kit setup. You need to
be able to force a consistent fail, to debug.

I would begin with looking at the output position of the op
amp and the input offset, at the condition. Your AVOL sim
depends on the amplifier being nulled, to get the (peak)
gain answer. If your initial condition is jacked, gain suffers
big time. Some testbenches will allow such an initial condition.

You may also want to place, alongside your design, some
PCM-equivalent test devices and bias networks that will
let you observe whether you are being "taxed" by bogus
individual-device attributes (i.e. ones that would be rejected
at WAT), or determine some relation between the MOS
device attributes and any circuit level misbehavior. You
want to pick off VT, subthreshold slope (although this is
seldom criticized), gm, and something for Rout (lambda,
Early voltage, whatever).