Hi, I need to design a differential Low-Noise Amplifier (LNA) using the IBM 90nm CMOS process with f0= 2.3 to 2.6GHz, Differential Rin= 100Ω; S11 < -15dB, Voltage gain ≥20 dB, NF ≤2dB, IIP3 ≥-5dBm.
can any one help how to proceed with the design meeting all the contrains with minimum power.
please help...
i am meeting all other specs except the S11
when i am trying to achive the require S11 over the band, i have to decrease the input Q of the circuit and this in turn increases the NF beyond 2dB.. what to do...
please help...
i am meeting all other specs except the S11
when i am trying to achive the require S11 over the band, i have to decrease the input Q of the circuit and this in turn increases the NF beyond 2dB.. what to do...
You cannot obtain NFmin and best S11 simultaneously.There is a always a compromise between these two.You may use a mathcing circuit after NF matching circuitry.