[moved] How to test SDLD simple programmable logic , FIFO memory, Eprom chips

[johnburford]

what can I use to read the files and then write the files to new blank chips?

D43256AC-12LL, Static RAM

TIBPAL16LL8-25CN, SPLD Simple Programmable Logic Devices

27C256-2 , CMOS EPROM chip

AM9128-10PC, Static RAM

EP310DC-2, 8 Macrocell EPLD , Altera

IDT 7201-LA120D, CMOS Asynchronous FIFO First in/First out dual port memory

IDT 6116 = 2K X 8 CMOS Asynchronous Static RAM

 

[KlausST]

Hi,

All your SRAMs and FIFOs will loos data when not powered.
In a running system you need a lot off effort to read the data... and disconnected the data is lost.
I don't hink this is usefull.

The EEPROM most likely has a parallel interface. It keeps data even when not powered. So it is possible to read out with a parallel programmer. You could also build your own EEPROM reader with different types of microcontrollers like AVR, 8051 family or PICs...

The ALTERA chip most likely hase EEPROM or FLASH memory cells, they keep the data even when not powered. Reading out maybe is possible with a serial interface (SPI type?). But they usualky have a read protection to prevent from copying the chip.

The SPLD keeps it's data when not powered. Usually no read out protection. You need a parallel programmer for it.

******
Read datasheets of the devices. Then try to find prgrammer for it. The chips you refer are old, so possibly you may find an old programmer on ebay. But often they need a parallel PC interface and software and old operating systems, maybe all this not running on modern PC hardware...

Good luck

Klaus