[Moved] how to know how big is a asci/fpga design?

[hjacky]

Hello, guys,

may i ask 1 naive questions:

1. how do you know the size of a asci or fpga design? when you say size, do you all mean the cell number or something else?

Thanks,

 

[TrickyDicky]

I think you mean asic, not asci.

1. Its difficult to compare asics and FPGA directly as the technology is so different. For FPGA, you are often interested in one or more of the following: LUT or register usage, meory usage or DSP usage. On more complex designs you might worry about clock resources too. Those are the three main components on an FPGA.

For Asic, you usually see numbers in terms of gate count.

 

[hjacky]

I think you mean asic, not asci.

1. Its difficult to compare asics and FPGA directly as the technology is so different. For FPGA, you are often interested in one or more of the following: LUT or register usage, meory usage or DSP usage. On more complex designs you might worry about clock resources too. Those are the three main components on an FPGA.

For Asic, you usually see numbers in terms of gate count.

Thanks for that!

I can further my questions like this:
I wonder if you have some tutorials to guide choosing FPGA chips?

To FPGA, it is more important to know how to choose a suitable FPGA, not too expensive, however, compatible for the logic;
For ASIC, it is more important to achieve the aggressive power and timing, area is becoming a insignificant cases in most scenarios;