[moved] How to clear Verilog HDL error

sugubai · Oct 22, 2017

Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
module kj(j1,l1,j,k,clock,reset,q,qb,q1,qb1,b);
input j1,l1,j,k,clock,reset;
output reg q1,qb1;
output reg [3:0]q,qb,b,a;
always@(negedge clock)
begin
case({reset,j1,l1})
3'b100 :q1=q1;
3'b101 :q1=0;
3'b110 :q1=1;
3'b111 :q1=~q1;
default :q1=0;
endcase
qb1<=~q1;
end
always@ *
begin
if(q1==q1)
begin
kl JK1(j,k,clock,reset,q[0],qb[0]);
kl JK2(j,k,q[0],reset,q[1],qb[1]);
kl JK3(j,k,q[1],reset,q[2],qb[2]);
kl JK4(j,k,q[2],reset,q[3],qb[3]);
end
end
else if(q1==0)
begin
kl JK5(j,k,d,reset,q[0],qb[0]);
kl JK6(j,k,q[0],reset,q[1],qb[1]);
kl JK7(j,k,q[1],reset,q[2],qb[2]);
kl JK8(j,k,q[2],reset,q[3],qb[3]);
end
 
else if(q1==1)
begin
always@(reset)
begin
if(reset)
q <=4'b0000;
else if(q<4'b0101)
q <= q+1;
else
b=q[1]&&q[3];
end
end
 
else if (q1==~q1)
begin
always@(posedge clock)
begin
if(reset)
q <=4'b0000;
else if(q<4'b0011)
q <= q+1;
else
a=q[2]&&q[3];
end
end
endmodule

this is my verilog code i have some error in this...

Error (10170): Verilog HDL syntax error at kj.v(20) near text "("; expecting ";", or ","
Error (10170): Verilog HDL syntax error at kj.v(20) near text ")"; expecting ";", or ","
Error (10170): Verilog HDL syntax error at kj.v(21) near text "("; expecting ";", or ","
Error (10149): Verilog HDL Declaration error at kj.v(21): identifier "k" is already declared in the present scope
Error (10149): Verilog HDL Declaration error at kj.v(21): identifier "q" is already declared in the present scope
Error (10149): Verilog HDL Declaration error at kj.v(21): identifier "reset" is already declared in the present scope
Error (10149): Verilog HDL Declaration error at kj.v(21): identifier "qb" is already declared in the present scope
Error (10170): Verilog HDL syntax error at kj.v(21) near text ")"; expecting ";", or ","
Error (10170): Verilog HDL syntax error at kj.v(22) near text "("; expecting ";", or ","
Error (10149): Verilog HDL Declaration error at kj.v(22): identifier "k" is already declared in the present scope
Error (10149): Verilog HDL Declaration error at kj.v(22): identifier "q" is already declared in the present scope
Error (10149): Verilog HDL Declaration error at kj.v(22): identifier "reset" is already declared in the present scope
Error (10149): Verilog HDL Declaration error at kj.v(22): identifier "qb" is already declared in the present scope
Error (10170): Verilog HDL syntax error at kj.v(22) near text ")"; expecting ";", or ","
Error (10170): Verilog HDL syntax error at kj.v(23) near text "("; expecting ";", or ","
Error (10149): Verilog HDL Declaration error at kj.v(23): identifier "k" is already declared in the present scope
Error (10149): Verilog HDL Declaration error at kj.v(23): identifier "q" is already declared in the present scope
Error (10149): Verilog HDL Declaration error at kj.v(23): identifier "reset" is already declared in the present scope
Error (10149): Verilog HDL Declaration error at kj.v(23): identifier "qb" is already declared in the present scope
Info: Found 0 design units, including 0 entities, in source file kj.v
Info: Generated suppressed messages file C:/altera/90/quartus/new/kl.map.smsg
Error: Quartus II Analysis & Synthesis was unsuccessful. 19 errors, 0 warnings
Error: Peak virtual memory: 218 megabytes
Error: Processing ended: Sun Oct 22 09:44:22 2017
Error: Elapsed time: 00:00:00
Error: Total CPU time (on all processors): 00:00:01
Error: Quartus II Full Compilation was unsuccessful. 21 errors, 0 warnings

my error is above mentioned please help

vGoodtimes · Oct 22, 2017

Re: How to clear Verilog HDL error

modules are instantiated outside of an always/initial block.

sugubai · Oct 22, 2017

Re: How to clear Verilog HDL error

vGoodtimes said:
modules are instantiated outside of an always/initial block.

Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
module kj(j1,l1,j,k,clock,reset,q,qb,q1,qb1,b);
input j1,l1,j,k,clock,reset;
output reg q1,qb1;
output reg [3:0]q,qb,b,a;
always@(negedge clock)
begin
case({reset,j1,l1})
3'b100 :q1=q1;
3'b101 :q1=0;
3'b110 :q1=1;
3'b111 :q1=~q1;
default :q1=0;
endcase
qb1<=~q1;
end
always@*
begin
if(q1==q1)
 
kl JK1(j,k,clock,reset,q[0],qb[0]);
kl JK2(j,k,q[0],reset,q[1],qb[1]);
kl JK3(j,k,q[1],reset,q[2],qb[2]);
kl JK4(j,k,q[2],reset,q[3],qb[3]);
end
always@*
begin
else if(q1==0)
 
kl JK5(j,k,clock,reset,q[0],qb[0]);
kl JK6(j,k,q[0],reset,q[1],qb[1]);
kl JK7(j,k,q[1],reset,q[2],qb[2]);
kl JK8(j,k,q[2],reset,q[3],qb[3]);
end
 
else if(q1==1)
begin
always@(reset)
begin
if(reset)
q <=4'b0000;
else if(q<4'b0101)
q <= q+1;
else
b=q[1]&&q[3];
end
end
 
else if (q1==~q1)
begin
always@(posedge clock)
begin
if(reset)
q <=4'b0000;
else if(q<4'b0011)
q <= q+1;
else
a=q[2]&&q[3];
end
end
endmodule

error

Error (10170): Verilog HDL syntax error at kj.v(20) near text "JK1"; expecting "<=", or "="
Error (10170): Verilog HDL syntax error at kj.v(21) near text "JK2"; expecting "<=", or "="
Error (10170): Verilog HDL syntax error at kj.v(22) near text "JK3"; expecting "<=", or "="
Error (10170): Verilog HDL syntax error at kj.v(23) near text "JK4"; expecting "<=", or "="
Error (10170): Verilog HDL syntax error at kj.v(27) near text "else"; expecting ";", or "@", or "end", or an identifier ("else" is a reserved keyword ), or a system task, or "{", or a sequential statement
Error (10170): Verilog HDL syntax error at kj.v(29) near text "JK5"; expecting "<=", or "="
Error (10170): Verilog HDL syntax error at kj.v(30) near text "JK6"; expecting "<=", or "="
Error (10170): Verilog HDL syntax error at kj.v(31) near text "JK7"; expecting "<=", or "="
Error (10170): Verilog HDL syntax error at kj.v(32) near text "JK8"; expecting "<=", or "="
Error (10170): Verilog HDL syntax error at kj.v(35) near text "else"; expecting an identifier ("else" is a reserved keyword ), or "endmodule", or a parallel statement
Error (10112): Ignored design unit "kj" at kj.v(1) due to previous errors

andre_luis · Oct 22, 2017

Re: How to clear Verilog HDL error

Besides the lack of indentation of the code, which denotes a certain sloppiness, there are several strange stuffs even for those who are not familiar with verilog language.

Code:

begin
else if(q1==0)

Code:

if(q1==q1)

If you really want to be helped, you have to make a little more effort to solve these problems by yourself

ads-ee · Oct 23, 2017

There are an excessive number of problems with this code, literally too many to point out.
To name just a few:

no formatting of the code
utterly useless names for everything (other than clock and reset)
lack of comments
non-Verilog 2001 port syntax
a case statement for a simple register description
using the negedge of a clock for no good reason
using always blocks for instantiating the k1 module
the earlier pointed out if (q1==q1), FYI this is always true

etc, there are more but, that is only half way through the file.

Apparently you don't understand that Verilog is a Hardware Description Language (HDL) and you should understand the logic you are trying to describe, not write any random code and hope it can be synthesized to logic.

vGoodtimes · Oct 23, 2017

IIRC, (q1 == q1) is false for q1 = 1'bx.

Code:

always@*
begin
if(q1==q1)
 
kl JK1(j,k,clock,reset,q[0],qb[0]);

modules are instantiated outside of an always/initial block.

ads-ee · Oct 23, 2017

vGoodtimes said:
IIRC, (q1 == q1) is false for q1 = 1'bx.

True but for synthesis this is always true and the logic that this if selects would always be done.

sugubai · Oct 25, 2017

Re: How to clear Verilog HDL error

Okk sir.. i am the beginner of the verilog so, now only i am just learned about it..anyway thank you sir

[moved] How to clear Verilog HDL error

sugubai

Newbie level 6

vGoodtimes

Advanced Member level 4

sugubai

Newbie level 6

andre_luis

Super Moderator

ads-ee

Super Moderator

vGoodtimes

Advanced Member level 4

ads-ee

Super Moderator

sugubai

Newbie level 6

Similar threads

[moved] How to clear Verilog HDL error

Newbie level 6

Advanced Member level 4

Newbie level 6

Super Moderator

Super Moderator

Advanced Member level 4

Super Moderator

Newbie level 6

Similar threads

Privacy & Transparency

Privacy & Transparency