[MOVED]how to bias nmos with a constant current source

[aarthy_maya]

hi all,

I am wondering how to bias a nmos/any device with constant current source. I tried connecting drain of mos to the current source and the other end of current source is connected to Vdd.(=1.8V), but when i try dc analysis with varying Vg, the drain voltage varies from 70V-0V, which i hope is not correct. can some one suggest me what is wrong with the method i followed, or any other effective way for current bias. (I am doing a very basic circuit, i hoped the circuit will function without trying current mirror and all).

thanks!!
Aarthy

 

[keith1200rs]

I think you need to give some more information - such as a circuit. I cannot visualise what you are trying to do. If you use a perfect current source in SPICE then it will generate whatever voltage is necessary to generate the desired current. If the circuit is not correctly defined then that can result in crazy voltages, taking devices into breakdown for example.

Keith.

 

[checkmate]

hi all,

I am wondering how to bias a nmos/any device with constant current source. I tried connecting drain of mos to the current source and the other end of current source is connected to Vdd.(=1.8V), but when i try dc analysis with varying Vg, the drain voltage varies from 70V-0V, which i hope is not correct. can some one suggest me what is wrong with the method i followed, or any other effective way for current bias. (I am doing a very basic circuit, i hoped the circuit will function without trying current mirror and all).

thanks!!
Aarthy

It's 100% correct.
Imagine if Vgs is zero, and you try to force 10uA into it's drain. What happens is that this current is forced into the MOS in the subthreshold region, and the only way this can occur is if the drain voltage is at insanely high voltages.
In real circuits, the current source will be replaced with a PMOS, which will be forced into the linear region if the NMOS cannot take the current, hence current sourced will be reduced.
If you want to bias a current, at least replace the current source with a PMOS current mirror.

 

[aarthy_maya]

thanks ppl..

But my doubt is wont setting the Vdd to 1.8V helps to limit the voltage across the device.

Sorry if i am wrong.

 

[checkmate]

The role of an ideal constant current source is very simple, which is to pass a constant current, ie 1uA.
If you load it with an ideal resistor to ground of say 1Gohm, you'll get 1kV.
It doesnt matter what terminal you tie the other end of the current source to.
By tieing the other terminal to Vdd, the only consequence will be that it will draw 1uA from vdd.