For the NMOS-input op-amp, when you bring the input common-mode between 0.3V and 0.59V and the bias transistor goes into triode, there is still current flowing through both MOSFETs in the diffpair, the circuit still has gain, and you still have negative feedback. However, the bias current decreases (because you no longer have full voltage across the bias transistor), which affects transconductance, frequency response, and offset voltage; also, because the bias transistor's output impedance decreases drastically, the CMRR and PSRR plummet. So although the op-amp might still function at this point, it doesn't function well.
I'm guessing that 0.3V is the NMOS threshold voltage in your process. Below this point, current essentially stops to flow, and the circuit ceases to function.
Hope this helps.