Hi,
I am using Xilinx kc705 board with VIVADO 15.2 for my project and project have several clocks. In report time summary "Total hold slack" doesn't meet the timing requirement. Therefore by means of "contraints wizard" I am trying to enter several constraints parameter.
For input there are clocks having colck period 37 ns, 10 ns, 15 ns .... and I am supposed to provide the value for following input delays parameters:
Similarly for output there are clocks having clock period 37 ns, 6 ns, 10 ns, 7 ns, ... and I am supposed to provide the value for following output delays parameters:
Code:
tsu, thd, trce_dly_max, trce_dly_min
But I don't know which value should I provide to these parameters. Where i can find such values?
the stuff inside a {} are collections in Tcl, which is what xdc/sdc is based on. Collections are just containers (lists) of stuff.
The first {} is specifying the clock pin of a specific register in the hierarchy.
The second {} is input to a regular expression that is looking for all the D pins of registers associated with a bus.
This constraint is probably for a cross clock domain register or they have a tighter requirement than the normal period constraint.