embeddedaebi
Junior Member level 1
Hello All !!!!!
I am trying to implement FIR filter on FPGA. I am not able make out how to go about it. I have calculated the coefficients and written a verilog code.There is 12 bit ADC which will provide the input. I am thinking of converting the 12 bit input into decimal, then apply the filter equation, then convert the answer into binary again to send to output.Now how to implement this is my concern. What should the test bench look like.
Please give some pointers as I am a newbie to both fpga and verilog.
Thanx in advance !!
I am trying to implement FIR filter on FPGA. I am not able make out how to go about it. I have calculated the coefficients and written a verilog code.There is 12 bit ADC which will provide the input. I am thinking of converting the 12 bit input into decimal, then apply the filter equation, then convert the answer into binary again to send to output.Now how to implement this is my concern. What should the test bench look like.
Please give some pointers as I am a newbie to both fpga and verilog.
Thanx in advance !!