[Moved] error in the following vhdl prog????

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this is my simple code for ADC.
Code VHDL - [expand]
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library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;
    use ieee.numeric_bit.all;
    use ieee.numeric_std;
    use ieee.std_logic_arith.all;
    
entity adc is
    port(clk:in std_logic;a:in std_logic_vector(15 downto 0);vout:out real);
end adc;
 
architecture a_body of adc is
    begin
        
        process(clk)
            begin
            if(clk='1')then
                Vout <= (3.3 * ((real((to_integer(unsigned(a)))) / 65535.0)));
            end if;
      end process;
      
    end a_body;




error in that code is........


pls give the idea to remove the error...
 
Last edited by a moderator:

this is because you have included both std_logic_arith and numeric_std packages. They both declare signed and unsigned types so the compiler doesnt know which one to use. The easiest fix is to remove the non-standard std_logic_arith package and use only numeric_std
 

Yes the problem in using library numeric and unsigned. u removed numeric and use only unsigned library. and your code having a real function. so ur having a another problem in real. real function cannot be synthesize in ISE. at that same time real synthesized inside of function in vhdl package declaration.
 

The code does require numeric_std library for to_integer(), so it shouldn't be removed. And it's generally better to use the true IEEE libraries.

Nothing is said about synthesis in the original post, it looks like a test bench DAC model (not ADC as claimed in the component name, because it has digital input and analog output). In this case, usage of real ports and functions won't be a problem.
 

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