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[moved] Error debugging in vhdl

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Ponmalar21

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Debug the error in the following verilog code:


Code Verilog - [expand]
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module ring_count(q,clk,clr); 
  input clk,clr; 
  output [3:0]q; 
  reg [3:0]q; 
  always @(posedge clk) 
      if(clr==1) 
            q<=4′b1000; 
        else 
            begin 
                q[3]<=q[0]; 
                q[2]<=q[3]; 
                q[1]<=q[2]; 
                q[0]<=q[1]; 
            end 
endmodule

 
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