[MOVED] efficient fpga realization of digital fir filter using distributed arithmetic

[MURALIMAHARAJAN]

my name muralimaharajan.p doing M.E vlsi design. i need a help from u verilog code for efficient fpga realization of digital fir filter using distributed arithmetic. i attach my block diagram

 

[TrickyDicky]

What help are you looking for?

 

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I think they want someone to write the code for them.

 

[TrickyDicky]

I think they want someone to write the code for them.

Surely not. Ive never seen that on this forum before....

 

[MURALIMAHARAJAN]

What help are you looking for?

i need an veriog code and vhdl code for this whole block diagram.

 

[TrickyDicky]

Oh The irony

If you need the code, then I suggest you start writing it then...

 

[ads-ee]

i need an veriog code and vhdl code for this whole block diagram.

I'm sure you can hire an FPGA/ASIC consulting firm from what comes up when you google it

 

[mrflibble]

i need an veriog code and vhdl code for this whole block diagram.

Thank you for restoring my faith in humanity. I got a good laugh out of that one. XD


Still chuckling. *grin*