[MOVED]Dynamic RAM in VHDL

[Ali Hamad]

Hi guys, I hope you are fine and happy
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I need help from you, please , I want to design dynamic RAM in VHDL, but befor that , I would like to anderstand StaticRAM ,so I did it BUT I could not simulat it so, I 'll show to you and if you have easier way than it, please show me it, thanks
this is source code ....... .

ibrary IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity tryRAM_sor is
generic( width: integer:=4;
depth: integer:=4;
addr: integer:=2);
Port ( clock : in STD_LOGIC;
enabl : in STD_LOGIC;
read_t : in STD_LOGIC;
write_t : in STD_LOGIC;
read_addr : in STD_LOGIC_VECTOR (1 downto 0);
write_addr : in STD_LOGIC_VECTOR (1 downto 0);
data_in : in STD_LOGIC_VECTOR (3 downto 0);
data_out : out STD_LOGIC_VECTOR (3 downto 0));
end tryRAM_sor;

architecture Behavioral of tryRAM_sor is

type ram_type is array (0 to depth-1) of
std_logic_vector(width-1 downto 0);
signal tmp_ram: ram_type;


begin

-- Read Functional Section
process(Clock, Read_t)
begin
if (Clock'event and Clock='1') then
if Enabl='1' then
if Read_t='1' then
-- buildin function conv_integer change the type
-- from std_logic_vector to integer
else
Data_out <= (Data_out'range => 'Z');
end if;
end if;
end if;
end process;

-- Write Functional Section
process(Clock, Write_t)
begin
if (Clock'event and Clock='1') then
if Enabl='1' then
if Write_t='1' then
end if;
end if;
end if;
end process;


end Behavioral;

This is test banch
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY tryRAM_tb IS
END tryRAM_tb;

ARCHITECTURE behavior OF tryRAM_tb IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT tryRAM_sor
PORT(
clock : IN std_logic;
enabl : IN std_logic;
read_t : IN std_logic;
write_t : IN std_logic;
read_addr : IN std_logic_vector(1 downto 0);
write_addr : IN std_logic_vector(1 downto 0);
data_in : IN std_logic_vector(3 downto 0);
data_out : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;


--Inputs
signal clock : std_logic := '0';
signal enabl : std_logic := '0';
signal read_t : std_logic := '0';
signal write_t : std_logic := '0';
signal read_addr : std_logic_vector(1 downto 0) := (others => '0');
signal write_addr : std_logic_vector(1 downto 0) := (others => '0');
signal data_in : std_logic_vector(3 downto 0) := (others => '0');

--Outputs
signal data_out : std_logic_vector(3 downto 0);

-- Clock period definitions
constant clock_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: tryRAM_sor PORT MAP (
clock => clock,
enabl => enabl,
read_t => read_t,
write_t => write_t,
read_addr => read_addr,
write_addr => write_addr,
data_in => data_in,
data_out => data_out
);
process
begin
Clock<='1'; -- clock cycle 10 ns
wait for 50 ns;
Clock<='0';
wait for 50 ns;
end process;

process

begin

enabl <= '1';
read_t <= '0';
write_t <= '0';
write_Addr <= ( Write_Addr'range => '0');
read_Addr <= ( Read_Addr'range => '0');
data_in <= ( Data_in'range => '0');
wait for 200 ns;

-- test write
for i in 0 to 3 loop
Write_Addr <= Write_Addr + "1";
Data_in <= Data_in + "10";
Write_t <= '1';
wait for 100 ns;
end loop ;
assert (T_Data_out="ZZZZ")


-- test read
for i in 0 to 2 loop
read_Addr <= (read_Addr + 1);
read_t <= '1';
wait for 100 ns;
end loop;


wait;

end process;

END;

 

[Ali Hamad]

i have tried to connect in this page , but i could not so, please, i need speed help BC i don't have time and this project is ( My Graduation Project)

 

[TrickyDicky]

once you post what your problems are, and be specific about them, maybe we can help. We're not here to do your graduation project for you.

 

[Ali Hamad]

first , I wrote ' this is my Graduation Project' to i tell you i do not have time that's it, then, i have never said to you do the project if you have information tell me , other ways do not give me Instructions

my problem is i can't sumilate it ,note, i have done many examples , thanks

 

[TrickyDicky]

why cant you simulate it?

 

[Ali Hamad]

hi man ... when I tried to simulate it ,I got two errors which were :

ERROR:HDLCompiler:806 - "C:/Users/ali/Documents/project/New_13.2/tryRAM_pro/tryRAM_tb.vhd" Line 118: Syntax error near "for".
ERROR:HDLCompiler:854 - "C:/Users/ali/Documents/project/New_13.2/tryRAM_pro/tryRAM_tb.vhd" Line 41: Unit <behavior> ignored due to previous errors.

line 118-----> for i in 0 to 2 loop
read_Addr <= (read_Addr + 1);
read_t <= '1';
wait for 100 ns;
end loop;

 

[TrickyDicky]

you have forgotten to put a semi-colon on the previous line. (please check the errors yourself).
Secondly, you are missing arithmatic libraries, so + will not work (it doesnt work with std_logic_vector anyway)

 

[Ali Hamad]

hi man , I'm grateful to you ....... it done know so I could simulated 1k*1k SRAM,
well , please I have guestion , I know there are differances in design between SRAM and DRAM . can you tell me what these are ? thanks