[moved] Dual MicroBlaze design in Xilinx EDK 10.1

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roshan12

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It is not possible to create a system design comprising of two MicroBlaze processors operating at the same time. I used the base system builder wizard in Xilinx EDK 10.1 to design the system. Initially I built a single processor system and then tried to add the second processor IP (from IP catalog). But when creating the netlist for the system the following error occured:


The issue I suppose was with clock signal not connected to the processor IP. I didn't find any options to connect the same. What might I be doing wrong??

P.S: the processors are not intended to be used as multi-cores. They should be individually operating embedded processors
 

There is nothing in Xilinx's tool chain AFAIK that precludes having multiple Microblaze processors in a design, Carefully check that you have a clock connected to both Microblaze.
 

For your information, 2 MB MCS can be used on vivado.
 

how can I check for the connection?
the ports tab in system assembly view window doesn't show any clock signal connections. also for my design the BSB generated a clock generator and sys_proc_reset module.

should I manually modify the MHS file to pt in necessary clock signals for the processors?

- - - Updated - - -

ads-ee said:
There is nothing in Xilinx's tool chain AFAIK that precludes having multiple Microblaze processors in a design, Carefully check that you have a clock connected to both Microblaze.
Click to expand...

how can I check for the connection?
the ports tab in system assembly view window doesn't show any clock signal connections. also for my design the BSB generated a clock generator and sys_proc_reset module.

should I manually modify the MHS file to pt in necessary clock signals for the processors?
 

roshan12 said:
should I manually modify the MHS file to pt in necessary clock signals for the processors?
Click to expand...

Do that as a test, and then read the new mhs-file back into the EDK tool.
Maybe you can see the clock signal and understand what mistake you did.
Then go back to your original mhs file and try to do the same thing.
 

std_match said:
Do that as a test, and then read the new mhs-file back into the EDK tool.
Maybe you can see the clock signal and understand what mistake you did.
Then go back to your original mhs file and try to do the same thing.
Click to expand...

Hi, when i checked the MHS file the Microblaze instances were mapped as follows:


the lines PARAMETER C_INTERCONNECT = 1 and were found to be missing in the Microblaze IP added afterwards.

I also tried to add an additional clock output to the clock generator.

what might i be missing?
 

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