[Moved]: Digital phase locked loop

Status
Not open for further replies.

hanikapa

Member level 4
Joined
Feb 6, 2015
Messages
71
Helped
0
Reputation
0
Reaction score
0
Trophy points
6
Activity points
510
Hello,
I want to learn about digital phase locked loop design. As far as I search, there are implementation about it in some thesis or articles which explain their main blocks like TDC, DCO,... I understannd their concepts but I have problem about the interface to connect this blocks. for example when it shoes there are encoders at the output of TDC, how is the implementation for that or the implementation of the registers? Can annybody introduce me a good reference that explains with detail the DPLL?
Thannks
 

This is a DPLL discussion for a specific DPLL chip, but it may help in your general understanding of the technique.
 

Status
Not open for further replies.
Cookies are required to use this site. You must accept them to continue using the site. Learn more…