I want to delay a variable-frequency square signal for about 50-100 us (too much time for implementing it with inverters). How can I do this? Maybe some kind of D-latch with other stuff?
Thanks!
PD: I don't have access to digital design-synthesis-P&R tools, so the design have to be implementable with analog layout tools.
I think that the delay time is quite long for an RC-delay. It would probably requiere a MOhm resistor and I am looking for a fully integrated solution.
Yeah, but the thing is, you can still use this if you don't really care too much about the accuracy of that active resistor (as long as the delay tolerance is acceptable to you). You could just bias it crudely using a dc gm biaser that tracks PVT.
Current starved inverters with per-stage capacitor loads
and resquaring buffers, are a common approach to DLL
(the RO / delay element). You need to think about how you
are going to maintain duty cycle fidelity, if you care about
that. I recommend you use inverting stages of uniform
design, noninverting stages accumulate duty cycle
distortion while inverting ones cancel.
I solved this issue with a fully digital circuit made up of a binary counter and a simple FSM. If I have time I'll upload a document just in case anyone has a similar problem.