[moved] D-Type Positive-Edge -Triggered Flip-Flop with discrete components?

[neazoi]

Hello, I would like to build this circuit 2-chip VFO + stabiliser but using a discrete flip flop.

Based on this:


I see that SD and RD are tied to VCC which means that the FF is positive edge trigered.
As I am only interested in one output (Q) is that possible to implement such a function using discrete components (eg just 1-2 multivibrators) , instead to trying to implement the whole FF gates using discrete components?

 

[FvM]

I presumed you would rather use a classical two-transistor flip-flop circuit for the frequency divider, as described here https://www.electronics-tutorials.ws/waveforms/bistable.html

 

[neazoi]

I presumed you would rather use a classical two-transistor flip-flop circuit for the frequency divider, as described here https://www.electronics-tutorials.ws/waveforms/bistable.html

The problem with it is that it does not have two inputs (clk, D) but just one.

 

[betwixt]

Without looking at the finer details, I would guess the first flip-flop is working as a divide by 2 with it's output and the 'D' input XOR'ed to produce 'Q'. The second flip-flop is working like an inverter.

Keep that red LED in the dark! It will change capacitance if light falls on it.

Brian.

 

[BradtheRad]

The link below describes a "complete type D flip-flop, in discrete circuitry."

A single input causes the toggle action. It requires ten transistors, plus several resistors and diodes.

The author (Tim Williams) calls it the "second most beautiful circuit I've ever drawn." He includes a tube based version. (Scroll halfway down.)

**broken link removed**

 

[FvM]

The problem with it is that it does not have two inputs (clk, D) but just one.

I presumed you wanted to use the circuit for a frequency divider. As I see it's a different application.

I guess, you can make a D-FF circuit with a dynamical clock input too, you don't necessarily need a master-slave circuit. But it will need more than two transistors.

- - - Updated - - -

To show the basic idea of a dynamic D-FF, I rearranged parts of T-FF circuit, adding an inverter.

The circuit is of course less perfect than "beautiful" post #5. It has large set-up and hold times and RC values may need adjustment for the actual clock speed.

 

[neazoi]

I presumed you wanted to use the circuit for a frequency divider. As I see it's a different application.

I guess, you can make a D-FF circuit with a dynamical clock input too, you don't necessarily need a master-slave circuit. But it will need more than two transistors.

- - - Updated - - -

To show the basic idea of a dynamic D-FF, I rearranged parts of T-FF circuit, adding an inverter.

The circuit is of course less perfect than "beautiful" post #5. It has large set-up and hold times and RC values may need adjustment for the actual clock speed.

This is short of what I was looking, thank you.
I am not interested in very high speed, 32KHz would be the clock and data inputs, do you think these values are ok for that frequency?

 

[FvM]

The simulation suggests that 32 kHz should be possible. But the setup time of the D input relative to clock can be critical.

 

[betwixt]

I would have thought so. The speed limitaton is primarily due to the internal RC time constants, including 'C' from parasitic capacitances. It will work down to low frequencies and I would guess up to 1MHz or more. An IC design would eliminate most of the resistances and clock coupling capacitors, hence being faster and not having a lower clock rise and fall time limitation.

Brian.

 

[neazoi]

The simulation suggests that 32 kHz should be possible. But the setup time of the D input relative to clock can be critical.

I am terribly sorry! I meant 32Hz not 32KHz
Will that be that critical at 32Hz?
excuse me!

 

[betwixt]

Less critical at 32Hz than 32KHZ!
The issue with the diagram in post #6 is the rise and fall time of the clock waveform. The logic level switching speed is primarily decided by the current that can flow through the resistors to charge the capacitances in the wiring and transistor junctions but the 'kick' it needs to switch state (flip to flop) relies on the charge on C1 and C2. The two transistors work like a steering mechanism, each preparing the other side for the next clock pulse but a slow rise will allow C1 and C2 to charge without drawing sufficient current to bias the 'waiting' transistor. If driven from a clean square wave it sould work fine.

Brian.

 

[FvM]

If driven from a clean square wave it should work fine.

Yes, if the clock is a sine waveform, I would spend a two-transistor schmitt-trigger inbetween.