Damomeera
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Hi All,
I have written behavioral coding for ALU. While creating schematic in design vision, the icon gets greyed out after compiling my design. Please help me with this problem.
Thank you.
I have written behavioral coding for ALU. While creating schematic in design vision, the icon gets greyed out after compiling my design. Please help me with this problem.
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 `timescale 1ns / 1ps //////////////////////////////////////////////////////////// module aluuu( a, b, status_in, op, clk, rst, status_out, //c0 is the Output bits for all operations. For Mul operations, output is {c1,c0} //as multiplication of two 16 bit number resuts in maximum of 32 bit number. c0, c1 ); input [15:0] a,b; input [3:0] status_in; input [3:0] op; input clk,rst; output [15:0] c0; output [15:0] c1; output [3:0] status_out; reg [3:0] status_out; // status register in test_bench - 0:Carry bit 1:Zero bit 2:Borrow bit 3:Parity bit reg [15:0] c0,c1; //Opcode written as parameters. parameter Add=4'b0000, Adc=4'b0001, Sub=4'b0010, Sbb=4'b0011, inc=4'b0100, dec=4'b0101, Mul=4'b0110, pst=4'b0111, And=4'b1000, Or =4'b1001, Not=4'b1010, Nan=4'b1011, Nor=4'b1100, Xor=4'b1101, Lst=4'b1110, Rst=4'b1111; function parity; input [15:0] c; begin parity=0; if(status_in[3]==0) begin parity = (status_in[3]^c0[0]^c0[1]^c0[2]^c0[3]^c0[4]^c0[5]^c0[6]^c0[7]^c0[8]^c0[9]^c0[10]^c0[11]^c0[12]^c0[13]^c0[14]^c0[15]); end else begin parity = (c0[0]^c0[1]^c0[2]^c0[3]^c0[4]^c0[5]^c0[6]^c0[7]^c0[8]^c0[9]^c0[10]^c0[11]^c0[12]^c0[13]^c0[14]^c0[15]); end end endfunction function zero_check; input [15:0]x,y; begin zero_check=0; if(x==0 && y ==0) begin zero_check= status_in[1] | 1; end else begin zero_check=status_in[1] & 0; end end endfunction //Beginning of the always block. always@(posedge clk) begin if(rst) begin c0=0; c1=0; status_out = status_in; end else begin case(op) Add:begin{status_out[0],c0} = a+b; c1=0; status_out[3]=parity(c0); status_out[1]=zero_check(c0,c1);end Adc:begin {status_out[0],c0} = a+b+status_in[0]; c1=0; status_out[3]=parity(c0); status_out[1]=zero_check(c0,c1);end Sub:begin c0 = a-b;c1=0;status_out[3]=parity(c0); status_out[1]=zero_check(c0,c1);if(b>a)begin status_out[2]=1; end else begin status_out[2]=0; end end Sbb:begin c0 = a-b-status_in[2]; c1=0;status_out[3]=parity(c0); status_out[1]=zero_check(c0,c1);if(b+status_in[2]>a)begin status_out[2]=1; end else begin status_out[2]=0; end end inc:begin {status_out[0],c0} = a+1;status_out[3]=parity(c0); status_out[1]=zero_check(c0,c1); end dec:begin c0 =a-1;status_out[3]=parity(c0); status_out[1]=zero_check(c0,c1); end Mul:begin {c1,c0} = a*b; status_out[3]=parity(c0); status_out[1]=zero_check(c0,c1);end pst:begin c0=a; c1 = 0;status_out[3]=parity(c0); status_out[1]=zero_check(c0,c1); end And:begin c0=a & b;status_out[3]=parity(c0); status_out[1]=zero_check(c0,c1); end Or: begin c0=a | b; status_out[3]=parity(c0); status_out[1]=zero_check(c0,c1);end Not:begin c0=~a; status_out[3]=parity(c0); status_out[1]=zero_check(c0,c1);end Nan:begin c0=~(a & b);status_out[3]=parity(c0); status_out[1]=zero_check(c0,c1); end Nor:begin c0=~(a | b);status_out[3]=parity(c0); status_out[1]=zero_check(c0,c1); end Xor:begin c0=a ^ b;status_out[3]=parity(c0); status_out[1]=zero_check(c0,c1); end Lst:begin c0=a<<b; status_out[3]=parity(c0); status_out[1]=zero_check(c0,c1);end Rst:begin c0=a>>b;status_out[3]=parity(c0); status_out[1]=zero_check(c0,c1); end default: $display("invalid entry"); endcase end end endmodule
Thank you.