module i2cio3(
input wire clk,
inout wire sda,
input wire reset,
output wire scl,
output reg [7:0] data,
output reg [7:0] state,
output wire i2c_clk
);
localparam STATE_IDLE =0; //00000
localparam STATE_START_WRITE =1; //00001
localparam STATE_I2C_ADD_CALL1 =2; //00010
localparam STATE_RW1 =3; //00011
localparam STATE_ACK1 =4; //00100
localparam STATE_REG_ADD1 =5; //00101
localparam STATE_ACK2 =6; //00110
localparam STATE_START_READ =7; //00111
localparam STATE_I2C_ADD_CALL2 =8; //01000
localparam STATE_RW2 =9; //01001
localparam STATE_ACK3 =10; //01010
localparam STATE_DATA =11; //01011
localparam STATE_ACK4 =12; //01100
localparam STATE_STOP =13; //01101
localparam STATE_REG_ADD =14; //01110
localparam STATE_WAIT1 =15; //01111
localparam STATE_WAIT2 =16; //10000
localparam STATE_WAIT3 =17; //10001
localparam STATE_WAIT4 =18; //10010
localparam STATE_WAIT5 =19; //10011
localparam STATE_WAIT6 =20; //10100
localparam STATE_IDLE2 =21; //10101
reg [7:0] addr;
reg [6:0] adcall;
reg [7:0] count;
reg ack1;
reg ack2;
reg ack3;
reg sda_reg;
reg scl_reg;
reg [1:0] scl_enable;
reg rw1;
reg rw2;
reg sclkcnt;
initial begin
scl_enable<=0;
sclkcnt <=1;
sda_reg<=1;
scl_reg<=1;
end
assign sda=sda_reg;
assign scl=scl_reg;
i2c_clk_divider instance_name (
.clk(clk),
.reset(reset),
.i2c_clk2(i2c_clk2),
.i2c_clk(i2c_clk)
);
// always @(i2c_clk)begin
// if(scl_enable==1) scl_reg<=~i2c_clk;
// else if(scl_enable==0) scl_reg<=1;
// else scl_reg<=0;
// end
always @(posedge i2c_clk2)begin
if(reset==1)begin
scl_enable<=0;
sda_reg<=1;
state<=STATE_IDLE;
adcall<=7'b0111001;
addr<=8'b10011000;//'h0x98;
rw1<=0;
rw2<=1;
data<=8'b10101010;
end
else begin
case(state)
STATE_IDLE:
begin //IDDLE
scl_enable<=0;
if(sclkcnt<=0)begin
state<=STATE_START_WRITE;
sclkcnt<=1;
scl_reg<=1;
sda_reg<=1;
end
else begin
sclkcnt<=sclkcnt-1;
scl_reg<=1;
sda_reg<=1;
end
end
STATE_START_WRITE:
begin //START
scl_enable <= 0;
count<=6;
if(sclkcnt<=0)begin
state<=STATE_WAIT1;
sclkcnt<=1;
sda_reg<=0;
scl_reg<=0;
end
else begin
sclkcnt<=sclkcnt-1;
sda_reg<=0;
scl_reg<=1;
end
end
STATE_WAIT1:
begin
sda_reg<=0;
scl_enable<=2;
if(sclkcnt<=0)begin
state<=STATE_I2C_ADD_CALL1;
sclkcnt<=1;
scl_reg<=0;
end
else begin
sclkcnt<=sclkcnt-1;
scl_reg<=0;
end
end
STATE_I2C_ADD_CALL1:
begin
scl_enable<=1;
sda_reg<=adcall[count];
if(count==0)begin
if(sclkcnt<=0)begin
state<=STATE_RW1;
sclkcnt<=1;
scl_reg<=~i2c_clk;
end
else begin
sclkcnt<=sclkcnt-1;
scl_reg<=~i2c_clk;
end
end else begin
if(sclkcnt<=0)begin
count<=count-1;
sclkcnt<=1;
scl_reg<=~i2c_clk;
end
else begin
sclkcnt<=sclkcnt-1;
scl_reg<=~i2c_clk;
end
end
end
STATE_RW1:
begin
scl_enable<=1;
count<=7;
sda_reg<=rw1;
if(sclkcnt<=0)begin
state<=STATE_ACK1;
sclkcnt<=1;
scl_reg<=~i2c_clk;
end
else begin
sclkcnt<=sclkcnt-1;
scl_reg<=~i2c_clk;
end
end
STATE_ACK1:
begin
scl_enable<=1;
sda_reg<=1;
if(sclkcnt<=0)begin
state<=STATE_WAIT2;
sclkcnt<=1;
scl_reg<=~i2c_clk;
end
else begin
sclkcnt<=sclkcnt-1;
scl_reg<=~i2c_clk;
end
end
STATE_WAIT2:
begin
scl_enable<=2;
sda_reg<=1;
if(sclkcnt<=0)begin
state<=STATE_REG_ADD1;
sclkcnt<=1;
scl_reg<=0;
end
else begin
sclkcnt<=sclkcnt-1;
scl_reg<=0;
end
end
STATE_REG_ADD1:
begin
sda_reg<=addr[count];
scl_enable<=1;
if(count==0)begin
if(sclkcnt<=0)begin
state<=STATE_ACK2;
sclkcnt<=1;
scl_reg<=~i2c_clk;
end
else begin
sclkcnt<=sclkcnt-1;
scl_reg<=~i2c_clk;
end
end else begin
if(sclkcnt<=0)begin
count<=count-1;
sclkcnt<=1;
scl_reg<=~i2c_clk;
end
else begin
sclkcnt<=sclkcnt-1;
scl_reg<=~i2c_clk;
end
end
end
STATE_ACK2:
begin
sda_reg<=1;
scl_enable<=1;
if(sclkcnt<=0)begin
state<=STATE_WAIT3;
sclkcnt<=1;
scl_reg<=~i2c_clk;
end
else begin
sclkcnt<=sclkcnt-1;
scl_reg<=~i2c_clk;
end
end
STATE_WAIT3:
begin
scl_enable<=0;
sda_reg<=1;
if(sclkcnt<=0)begin
state<=STATE_START_READ;
sclkcnt<=1;
scl_reg<=1;
end
else begin
sclkcnt<=sclkcnt-1;
scl_reg<=1;
end
end
STATE_START_READ:
begin
sda_reg<=0;
scl_enable<=1;
count<=6;
if(sclkcnt<=0)begin
state<=STATE_WAIT4;
sclkcnt<=1;
scl_reg<=0;
end
else begin
sclkcnt<=sclkcnt-1;
scl_reg<=1;
end
end
STATE_WAIT4:
begin
scl_enable<=2;
sda_reg<=1;
if(sclkcnt<=0)begin
state<=STATE_I2C_ADD_CALL2;
sclkcnt<=1;
scl_reg<=0;
end
else begin
sclkcnt<=sclkcnt-1;
scl_reg<=0;
end
end
STATE_I2C_ADD_CALL2:
begin
scl_enable<=1;
sda_reg<=adcall[count];
if(count==0)begin
if(sclkcnt<=0)begin
state<=STATE_RW2;
sclkcnt<=1;
scl_reg<=~i2c_clk;
end
else begin
sclkcnt<=sclkcnt-1;
scl_reg<=~i2c_clk;
end
end else begin
if(sclkcnt<=0)begin
count<=count-1;
sclkcnt<=1;
scl_reg<=~i2c_clk;
end
else begin
sclkcnt<=sclkcnt-1;
scl_reg<=~i2c_clk;
end
end
end
STATE_RW2:
begin //BIT 5
sda_reg<=rw2;
scl_enable<=1;
if(sclkcnt<=0)begin
state<=STATE_ACK3;
sclkcnt<=1;
scl_reg<=~i2c_clk;
end
else begin
sclkcnt<=sclkcnt-1;
scl_reg<=~i2c_clk;
end
end
STATE_ACK3:
begin
sda_reg<=1;
scl_enable<=1;
count<=7;
if(sclkcnt<=0)begin
state<=STATE_WAIT5;
sclkcnt<=1;
scl_reg<=~i2c_clk;
end
else begin
sclkcnt<=sclkcnt-1;
scl_reg<=~i2c_clk;
end
end
STATE_WAIT5:
begin
scl_enable<=2;
sda_reg<=1;
if(sclkcnt<=0)begin
state<=STATE_DATA;
sclkcnt<=1;
scl_reg<=0;
end
else begin
sclkcnt<=sclkcnt-1;
scl_reg<=0;
end
end
STATE_DATA:
begin
sda_reg<=1;
scl_enable<=1;
data[count]<=sda_reg;
if(count==0)begin
if(sclkcnt<=0)begin
state<=STATE_ACK4;
sclkcnt<=1;
scl_reg<=~i2c_clk;
end
else begin
sclkcnt<=sclkcnt-1;
scl_reg<=~i2c_clk;
end
end else begin
if(sclkcnt<=0)begin
count<=count-1;
sclkcnt<=1;
scl_reg<=~i2c_clk;
end
else begin
sclkcnt<=sclkcnt-1;
scl_reg<=~i2c_clk;
end
end
end
STATE_ACK4:
begin
sda_reg<=0;
scl_enable<=1;
if(sclkcnt<=0)begin
state<=STATE_WAIT6;
sclkcnt<=1;
scl_reg<=~i2c_clk;
end
else begin
sclkcnt<=sclkcnt-1;
scl_reg<=~i2c_clk;
end
end
STATE_WAIT6:
begin
scl_enable<=2;
sda_reg<=1;
if(sclkcnt<=0)begin
state<=state<=STATE_STOP;
sclkcnt<=1;
scl_reg<=0;
end
else begin
sclkcnt<=sclkcnt-1;
scl_reg<=0;
end
end
STATE_STOP:
begin
sda_reg<=1;
scl_enable<=0;
state<=STATE_IDLE;
end
endcase
end//end else
end // end always
endmodule
As an input, set it to 'Z' and the slave will drive it to '0' or let the pullup to bring it to '1'.
module i2cio3(
input wire clk,
inout wire sda,
input wire reset,
output wire scl,
output reg [7:0] data,
output reg [7:0] state,
output wire i2c_clk
);
localparam STATE_IDLE =0; //00000
localparam STATE_START_WRITE =1; //00001
localparam STATE_I2C_ADD_CALL1 =2; //00010
localparam STATE_RW1 =3; //00011
localparam STATE_ACK1 =4; //00100
localparam STATE_REG_ADD1 =5; //00101
localparam STATE_ACK2 =6; //00110
localparam STATE_START_READ =7; //00111
localparam STATE_I2C_ADD_CALL2 =8; //01000
localparam STATE_RW2 =9; //01001
localparam STATE_ACK3 =10; //01010
localparam STATE_DATA =11; //01011
localparam STATE_ACK4 =12; //01100
localparam STATE_STOP =13; //01101
localparam STATE_REG_ADD =14; //01110
localparam STATE_WAIT1 =15; //01111
localparam STATE_WAIT2 =16; //10000
localparam STATE_WAIT3 =17; //10001
localparam STATE_WAIT4 =18; //10010
localparam STATE_WAIT5 =19; //10011
localparam STATE_WAIT6 =20; //10100
localparam STATE_IDLE2 =21; //10101
localparam STATE_REPEATED_START =22; //10110
localparam STATE_WAIT7 =23;
reg [7:0] addr;
reg [6:0] adcall;
reg [7:0] count;
reg ack1;
reg ack2;
reg ack3;
reg sda_reg;
reg scl_reg;
reg [1:0] scl_enable;
reg rw1;
reg rw2;
reg [3:0] sclkcnt;
initial begin
scl_enable<=0;
sclkcnt <=3;
sda_reg<=1;
scl_reg<=1;
end
assign sda=(sda_reg==1)? 1'bz:1'b0;
assign scl=(scl_reg==1)? 1'bz:1'b0;
i2c_clk_divider instance_name (
.clk(clk),
.reset(reset),
.i2c_clk2(i2c_clk2),
.i2c_clk(i2c_clk)
);
// always @(i2c_clk)begin
// if(scl_enable==1) scl_reg<=~i2c_clk;
// else if(scl_enable==0) scl_reg<=1;
// else scl_reg<=0;
// end
always @(posedge i2c_clk2)begin
if(reset==1)begin
scl_enable<=0;
sda_reg<=1;
state<=STATE_IDLE;
adcall<=7'b0111001;
addr<=8'b10011001;//'h0x98;
rw1<=0;
rw2<=1;
data<=8'b11111111;
end
else begin
case(state)
STATE_IDLE:
begin
if(sclkcnt<=0)begin
state<=STATE_START_WRITE;
sclkcnt<=3;
scl_reg<=1;
sda_reg<=1;
end
else begin
sclkcnt<=sclkcnt-1;
scl_reg<=1;
sda_reg<=1;
end
end
STATE_START_WRITE:
begin //START
scl_enable <= 0;
count<=6;
if(sclkcnt==3)begin
sda_reg<=1;
sclkcnt<=sclkcnt-1;
scl_reg<=1;
end else if(sclkcnt==2)begin
sda_reg<=0;
sclkcnt<=sclkcnt-1;
scl_reg<=1;
end else if(sclkcnt==1)begin
sclkcnt<=sclkcnt-1;
scl_reg<=1;
sda_reg<=0;
end else begin
sclkcnt<=3;
scl_reg<=0;
sda_reg<=0;
state<=STATE_WAIT1;
end
end
STATE_WAIT1:
begin
sda_reg<=0;
scl_enable<=2;
if(sclkcnt<=0)begin
state<=STATE_I2C_ADD_CALL1;
sclkcnt<=3;
scl_reg<=0;
end else begin
sclkcnt<=sclkcnt-1;
scl_reg<=0;
end
end
STATE_I2C_ADD_CALL1:
begin
scl_enable<=1;
if(count==0)begin
if(sclkcnt==3)begin
sclkcnt<=sclkcnt-1;
scl_reg<=0;
sda_reg<=adcall[count];
end else if(sclkcnt==2)begin
sclkcnt<=sclkcnt-1;
scl_reg<=1;
end else if(sclkcnt==1)begin
sclkcnt<=sclkcnt-1;
scl_reg<=1;
end else begin
state<=STATE_RW1;
sclkcnt<=3;
scl_reg<=0;
end
end else begin
if(sclkcnt==3)begin
sclkcnt<=sclkcnt-1;
scl_reg<=0;
sda_reg<=adcall[count];
end else if(sclkcnt==2)begin
sclkcnt<=sclkcnt-1;
scl_reg<=1;
end else if(sclkcnt==1)begin
sclkcnt<=sclkcnt-1;
scl_reg<=1;
end else begin
sclkcnt<=3;
scl_reg<=0;
count<=count-1;
end
end
end
STATE_RW1:
begin
scl_enable<=1;
count<=7;
if(sclkcnt==3)begin
sda_reg<=rw1;
sclkcnt<=sclkcnt-1;
scl_reg<=0;
end else if(sclkcnt==2)begin
sclkcnt<=sclkcnt-1;
scl_reg<=1;
end else if(sclkcnt==1)begin
sclkcnt<=sclkcnt-1;
scl_reg<=1;
end else begin
sclkcnt<=3;
scl_reg<=0;
state<=STATE_ACK1;
end
end
STATE_ACK1:
begin
scl_enable<=1;
sda_reg<=1;
if(sclkcnt==3)begin
sclkcnt<=sclkcnt-1;
scl_reg<=0;
end else if(sclkcnt==2)begin
sclkcnt<=sclkcnt-1;
scl_reg<=1;
end else if(sclkcnt==1)begin
sclkcnt<=sclkcnt-1;
scl_reg<=1;
end else begin
sclkcnt<=3;
scl_reg<=0;
state<=STATE_WAIT2;
end
end
STATE_WAIT2:
begin
scl_enable<=2;
if(sclkcnt==3)begin
sclkcnt<=sclkcnt-1;
sda_reg<=0;
scl_reg<=0;
end else if(sclkcnt==2)begin
sclkcnt<=sclkcnt-1;
scl_reg<=0;
end else if(sclkcnt==1)begin
sclkcnt<=sclkcnt-1;
scl_reg<=0;
end else begin
sclkcnt<=3;
scl_reg<=0;
state<=STATE_REG_ADD1;
end
end
STATE_REG_ADD1:
begin
scl_enable<=1;
if(count==0)begin
if(sclkcnt==3)begin
sclkcnt<=sclkcnt-1;
scl_reg<=0;
sda_reg<=addr[count];
end else if(sclkcnt==2)begin
sclkcnt<=sclkcnt-1;
scl_reg<=1;
end else if(sclkcnt==1)begin
sclkcnt<=sclkcnt-1;
scl_reg<=1;
end else begin
state<=STATE_ACK2;
sclkcnt<=3;
scl_reg<=0;
end
end else begin
if(sclkcnt==3)begin
sclkcnt<=sclkcnt-1;
scl_reg<=0;
sda_reg<=addr[count];
end else if(sclkcnt==2)begin
sclkcnt<=sclkcnt-1;
scl_reg<=1;
end else if(sclkcnt==1)begin
sclkcnt<=sclkcnt-1;
scl_reg<=1;
end else begin
sclkcnt<=3;
scl_reg<=0;
count<=count-1;
end
end
end
STATE_ACK2:
begin
scl_enable<=1;
sda_reg<=1;
if(sclkcnt==3)begin
sclkcnt<=sclkcnt-1;
scl_reg<=0;
end else if(sclkcnt==2)begin
sclkcnt<=sclkcnt-1;
scl_reg<=1;
end else if(sclkcnt==1)begin
sclkcnt<=sclkcnt-1;
scl_reg<=1;
end else begin
sclkcnt<=3;
scl_reg<=0;
state<=STATE_WAIT3;
end
end
STATE_WAIT3:
begin
scl_enable<=0;
if(sclkcnt==3)begin
sclkcnt<=sclkcnt-1;
scl_reg<=0;
sda_reg<=0;
end else if(sclkcnt==2)begin
sclkcnt<=sclkcnt-1;
scl_reg<=0;
sda_reg<=0;
end else if(sclkcnt==1)begin
sclkcnt<=sclkcnt-1;
scl_reg<=0;
sda_reg<=1;
end else begin
sclkcnt<=3;
scl_reg<=0;
sda_reg<=1;
state<=STATE_REPEATED_START;
end
end
STATE_REPEATED_START:
begin
scl_enable<=0;
if(sclkcnt==3)begin
sclkcnt<=sclkcnt-1;
sda_reg<=1;
scl_reg<=0;
end else if(sclkcnt==2)begin
sclkcnt<=sclkcnt-1;
sda_reg<=1;
scl_reg<=1;
end else if(sclkcnt==1)begin
sclkcnt<=sclkcnt-1;
scl_reg<=1;
sda_reg<=1;
end else begin
sclkcnt<=3;
scl_reg<=1;
sda_reg<=1;
state<=STATE_START_READ;
end
end
STATE_START_READ:
begin
count<=6;
if(sclkcnt==3)begin
sda_reg<=1;
sclkcnt<=sclkcnt-1;
scl_reg<=1;
end else if(sclkcnt==2)begin
sda_reg<=0;
sclkcnt<=sclkcnt-1;
scl_reg<=1;
end else if(sclkcnt==1)begin
sclkcnt<=sclkcnt-1;
scl_reg<=1;
sda_reg<=0;
end else begin
sclkcnt<=3;
scl_reg<=0;
sda_reg<=0;
state<=STATE_WAIT4;
end
end
STATE_WAIT4:
begin
sda_reg<=0;
if(sclkcnt<=0)begin
state<=STATE_I2C_ADD_CALL2;
sclkcnt<=3;
scl_reg<=0;
end else begin
sclkcnt<=sclkcnt-1;
scl_reg<=0;
end
end
STATE_I2C_ADD_CALL2:
begin
if(count==0)begin
if(sclkcnt==3)begin
sclkcnt<=sclkcnt-1;
scl_reg<=0;
sda_reg<=adcall[count];
end else if(sclkcnt==2)begin
sclkcnt<=sclkcnt-1;
scl_reg<=1;
end else if(sclkcnt==1)begin
sclkcnt<=sclkcnt-1;
scl_reg<=1;
end else begin
state<=STATE_RW2;
sclkcnt<=3;
scl_reg<=0;
end
end else begin
if(sclkcnt==3)begin
sclkcnt<=sclkcnt-1;
scl_reg<=0;
sda_reg<=adcall[count];
end else if(sclkcnt==2)begin
sclkcnt<=sclkcnt-1;
scl_reg<=1;
end else if(sclkcnt==1)begin
sclkcnt<=sclkcnt-1;
scl_reg<=1;
end else begin
sclkcnt<=3;
scl_reg<=0;
count<=count-1;
end
end
end
STATE_RW2:
begin
if(sclkcnt==3)begin
sda_reg<=rw2;
sclkcnt<=sclkcnt-1;
scl_reg<=0;
end else if(sclkcnt==2)begin
sclkcnt<=sclkcnt-1;
scl_reg<=1;
end else if(sclkcnt==1)begin
sclkcnt<=sclkcnt-1;
scl_reg<=1;
end else begin
sclkcnt<=3;
scl_reg<=0;
state<=STATE_ACK3;
end
end
STATE_ACK3:
begin
count<=7;
sda_reg<=1;
if(sclkcnt==3)begin
sclkcnt<=sclkcnt-1;
scl_reg<=0;
end else if(sclkcnt==2)begin
sclkcnt<=sclkcnt-1;
scl_reg<=1;
end else if(sclkcnt==1)begin
sclkcnt<=sclkcnt-1;
scl_reg<=1;
end else begin
sclkcnt<=3;
scl_reg<=0;
state<=STATE_WAIT5;
end
end
STATE_WAIT5:
begin
count<=7;
if(sclkcnt==3)begin
sclkcnt<=sclkcnt-1;
sda_reg<=0;
scl_reg<=0;
end else if(sclkcnt==2)begin
sclkcnt<=sclkcnt-1;
scl_reg<=0;
end else if(sclkcnt==1)begin
sclkcnt<=sclkcnt-1;
scl_reg<=0;
end else begin
sclkcnt<=3;
scl_reg<=0;
state<=STATE_DATA;
end
end
STATE_DATA:
begin
if(count==0)begin
if(sclkcnt==3)begin
sclkcnt<=sclkcnt-1;
scl_reg<=0;
sda_reg<=1;
end else if(sclkcnt==2)begin
sclkcnt<=sclkcnt-1;
scl_reg<=1;
sda_reg<=1;
end else if(sclkcnt==1)begin
sclkcnt<=sclkcnt-1;
scl_reg<=1;
sda_reg<=1;
end else begin
state<=STATE_ACK4;
sclkcnt<=3;
scl_reg<=0;
sda_reg<=1;
end
end else begin
if(sclkcnt==3)begin
sclkcnt<=sclkcnt-1;
scl_reg<=0;
sda_reg<=1;
end else if(sclkcnt==2)begin
sclkcnt<=sclkcnt-1;
scl_reg<=1;
sda_reg<=1;
end else if(sclkcnt==1)begin
sclkcnt<=sclkcnt-1;
scl_reg<=1;
sda_reg<=1;
end else begin
sclkcnt<=3;
sda_reg<=1;
scl_reg<=0;
count<=count-1;
end
end
end
STATE_ACK4:
begin
if(sclkcnt==3)begin
sda_reg<=1;
sclkcnt<=sclkcnt-1;
scl_reg<=0;
end else if(sclkcnt==2)begin
sclkcnt<=sclkcnt-1;
scl_reg<=1;
end else if(sclkcnt==1)begin
sclkcnt<=sclkcnt-1;
scl_reg<=1;
end else begin
sclkcnt<=3;
scl_reg<=0;
state<=STATE_WAIT6;
end
end
STATE_WAIT6:
begin
scl_enable<=0;
if(sclkcnt==3)begin
sclkcnt<=sclkcnt-1;
sda_reg<=0;
scl_reg<=0;
end else if(sclkcnt==2)begin
sclkcnt<=sclkcnt-1;
sda_reg<=0;
scl_reg<=0;
end else if(sclkcnt==1)begin
sclkcnt<=sclkcnt-1;
scl_reg<=0;
sda_reg<=0;
end else begin
sclkcnt<=3;
scl_reg<=0;
sda_reg<=0;
state<=STATE_STOP;
end
end
STATE_STOP:
begin
if(sclkcnt==3)begin
sclkcnt<=sclkcnt-1;
sda_reg<=0;
scl_reg<=1;
end else if(sclkcnt==2)begin
sclkcnt<=sclkcnt-1;
sda_reg<=0;
scl_reg<=1;
end else if(sclkcnt==1)begin
sclkcnt<=sclkcnt-1;
scl_reg<=1;
sda_reg<=1;
end else begin
sclkcnt<=3;
scl_reg<=1;
sda_reg<=1;
state<=STATE_IDLE;
end
end
endcase
end//end else
end // end always
endmodule
I defined scl high-z or 0.
assign sda=(sda_reg==1)? 1'bz:1'b0;
assign scl=(scl_reg==1)? 1'bz:1'b0;
I defined scl high-z or 0.
assign sda=(sda_reg==1)? 1'bz:1'b0;
assign scl=(scl_reg==1)? 1'bz:1'b0;
It should be high when no data transfer.
You should also read the I2C spec. It's never driven high it's always set to Hi-Z and a pullup is used to generate a high, the I2C is only driven low.
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?