Bagherieda
Newbie level 3
Hi,
I am trying to build a simplified model of a MOSFET to decrease the simulation time for the optimization of an Analog circuit. For this purpose, I have been going through the BSIM4 manual to extract the MOSFET modeling equations. Yet, for some of the intermediate parameters, I see a huge (and unreasonable) difference between the calculation result and the Cadence (Spectre) simulation one, for instance Vdsat. The formula to calculate Vdsat in the BSIM4 manual is (for Rds=0)
Vdsat=(Vgs-Vth+2vt)/(Abulk+(Vgs-Vth+2vt)/Esat*L)
where Esat=2VSAT/ueff and vt is the thermal voltage. Using the TSMC modeling parameters for an nMOS with sizing of W=1um and L=40nm, Abulk and ueff are calculated to be Abulk=1.17 and ueff=0.0188m^2/V.s. VSAT is 99710.81m/s. This gives Esat*L=0.466. With the transistor biased at Vgs=0.8V (Vth=581mV), Vdsat is calculated to be 154mV! This is already unreasonable because Vdsat must be close to Vgh-Vth. Indeed, because the value of Esat*L is always around 0.5, Vdsat happens to be much less than Vgs-Vth. The simulation tool gives me the realistic value of 215mV. Is this the formula that the simulation tools are using for Vdsat? Is there something that BSIM manual is not revealing?
The results become even more bizarre when you see that for a nMOS of W=200nm, VSAT is negative (VSAT=-103017.43) in the TSMC model library. Abulk is also calculated to be around 0.2 (shouldn't Abulk be very close to 1 for small channel length transistors?)!
I do not really understand what is going on here! I suspect BSIM manual is not telling everything and the way the device is modeled in the tools is somehow different. Does anybody here know the answer? I would be very grateful.
Kind regards,
Mojtaba
I am trying to build a simplified model of a MOSFET to decrease the simulation time for the optimization of an Analog circuit. For this purpose, I have been going through the BSIM4 manual to extract the MOSFET modeling equations. Yet, for some of the intermediate parameters, I see a huge (and unreasonable) difference between the calculation result and the Cadence (Spectre) simulation one, for instance Vdsat. The formula to calculate Vdsat in the BSIM4 manual is (for Rds=0)
Vdsat=(Vgs-Vth+2vt)/(Abulk+(Vgs-Vth+2vt)/Esat*L)
where Esat=2VSAT/ueff and vt is the thermal voltage. Using the TSMC modeling parameters for an nMOS with sizing of W=1um and L=40nm, Abulk and ueff are calculated to be Abulk=1.17 and ueff=0.0188m^2/V.s. VSAT is 99710.81m/s. This gives Esat*L=0.466. With the transistor biased at Vgs=0.8V (Vth=581mV), Vdsat is calculated to be 154mV! This is already unreasonable because Vdsat must be close to Vgh-Vth. Indeed, because the value of Esat*L is always around 0.5, Vdsat happens to be much less than Vgs-Vth. The simulation tool gives me the realistic value of 215mV. Is this the formula that the simulation tools are using for Vdsat? Is there something that BSIM manual is not revealing?
The results become even more bizarre when you see that for a nMOS of W=200nm, VSAT is negative (VSAT=-103017.43) in the TSMC model library. Abulk is also calculated to be around 0.2 (shouldn't Abulk be very close to 1 for small channel length transistors?)!
I do not really understand what is going on here! I suspect BSIM manual is not telling everything and the way the device is modeled in the tools is somehow different. Does anybody here know the answer? I would be very grateful.
Kind regards,
Mojtaba
