[Moved]: A problem in ultra-low VDD chip tesiing

[czq1419]

I'm testing my ultra-low VDD image sensor chip, and the on-chip LDO can provide a minimum output of 0.6V. Now I wanna further decrease the VDD to 0.4V to see if it still works. The question is how to generate this 0.4V VDD?
Current drawn from this VDD is uA level.
Thanks alot for reply.

 

[diligence]

Re: A problem in ultra-low VDD chip tesiing

Assuming you can use a external supply to source your sensor chip:

My suggestion is to try using a analog output pin of a DAQ board (example Daq boards from National Instruments)
You can generate 0.4 Volts and also since your chip draws uA of current, it means its input resistance is high. Hence any supply you use is going to source current in the range of uA as the input resistance is in the range of few Mega ohms and hence it draws uA of current from the supply.

Even a normal power supply should be good enough, but it might not have an indication of the current drawn by your sensor chip, since its in the range of micro Amperes. Same is the case with the Daq boards, but the difference is most the Daq boards analog output pin cannot source a lot of current, its usually in the range of 1 to 15 mA (depends on which model/type of Daq boards)

 

[D.A.(Tony)Stewart]

Re: A problem in ultra-low VDD chip tesiing

I thought it was the LDO that was 0.6V not Vdd. In any case you just want to generate a low voltage with a uA load? How about 3V and a resistor divider?

 

[KlausST]

Re: A problem in ultra-low VDD chip tesiing

Hi,

or an OPAMP.

Klaus