[Moved]: 5th Order Discrete Time Sigma Delta Modulator

[Puppet123]

Hello,

I am designing a 5th Order Sigma Delta Modulator - Discrete Time, with Single Bit Quantization.

I am following the procedures of:Understanding Delta-Sigma Data Converters by Temes.

In the text, they have example of 5th order modulator with following schematic, attached here.



My question is in regards to capacitor selection.

The book talks about the capacitor ratios but not about the actual values of the capacitors in the system themselves. How does one go about selecting and sizing the capacitors in this 5th order discrete time delta sigma modulator ?

Thanks.

 

[BradtheRad]

Re: 5th Order Discrete Time Sigma Delta Modulator

Small Farad values require small current to respond quickly at a given frequency, that is, to show large voltage change.

Large values in similar situation respond slightly, that is, display small voltage change.

 

[Puppet123]

Re: 5th Order Discrete Time Sigma Delta Modulator

Thank you for your response.

But are the selections of the actual capacitors made in an ad-hoc fashion or in a systematic fashion using simulation or using equations ?

 

[BradtheRad]

From your schematic it appears you switch capacitors in and out of circuit. I suppose they charge and discharge through mosfets? However the RC time constant cannot be known by looking at an icon of a mosfet. A simulator makes it easy to test different values.

Create a simulation of one or two RC charging-and-discharging circuits. As a guess, reckon on 1 mA going through 1 kOhm. (These are merely round figures as occur in low power circuits.) Does the capacitor display the expected waveform? Does it clip? Does it stay in the desired polarity?

There is a good reason to start with simple experiments. It's how we usually need to work with hardware, assembling modules rather than jumping immediately to a complex project. If you wish, you can fill in the same value for all capacitors, but then it is no fun to change values of 50 capacitors between each simulation run. Of course it is possible to edit a netlist directly, once you recognize which component is on which line, and which parameter is which.

 

[ZoOneR]

Hi,
The capacitors in sigma delta converters(SDM) are choesen by the required SNR. The main contributor to the total thermal nosie (assuming it is the dominant one) is the first integrator. Since you are using switched capacitor circuits the input referred noise is of the form kT/C, where C is the sampling capacitor. Knowing your required SNR, you can calculate the input referred noise, and than the required capacitance.
I think this article might be of help: "Design-Oriented Estimation of Thermal Noise in Switched-Capacitor Circuits" by Richard Schreier and Gabor C. Temes

 

[Puppet123]

Hello,

Yes, I am using the Temes/Schreier book actually and that is where that figure I attached came from.

The book works through an example for a 5th order modulator and comes up with capacitor ratios.

I have included the schematic again and the table generated in the book.

My main question is - how is CT from table (which is sum of C13 and C18) sized ?

Thanks.

 

[erikl]

My main question is - how is CT from table (which is sum of C13 and C18) sized ?

This depends on your process size, i.e. on the input (and partly on the output) capacitances of your diff amps. And on your required SNR.

 

[ZoOneR]

Hi,
In the picture it says that CT is the sum of C13 and other capacitances. But i find it odd that a1=C13/CT=2.25, since C13 should be smaller than CT. From what I remember, what Schreier does in his book is something like this.Knowing the SNR he deduces the wanted input referred noise. Than he calculates the contribution of each stage on the input noise. After this, he has some noise bugget that he divides to each stage. For example: 70% of noise will be caused by the input stage, 15% by the second stage, etc... After this he says that the noise of OpAmps is neglijable and all the noise comes from KT/C. Knowing the noise for each stage, and that it is equal to KT/C he calculates the sampling capacitances. Than he uses the coefficients to find the integrating capacitances.
I woul do the same. If this is the first time you do a SDM, I think a better practice is to begin with a simpler architecture, 2nd order for example.

 

[erikl]

In the picture it says that CT is the sum of C13 and other capacitances. But i find it odd that a1=C13/CT=2.25, since C13 should be smaller than CT.

@ZoOneR: In this case, CT isn't the smallest cap, but the sum of (C13..C18), as you correctly stated above. Here CT=8 ; the smallest caps of these are C17 & C18 with a value of C_17,18 = CT*3/4 = 6 .

@Puppet123: E.g. for a 0.18µm process size, I'd choose CT=1pf. So your smallest "standard" cap would be Cstd=CT/4=0.25pF. This means C13=9*Cstd, down to C17=C18=3*Cstd , i.e. for C13..C18 you'd need (an array of) 32*Cstd=8*CT .

 

[Puppet123]

Zooner, Erikl, thank you for your responses. I appreciate them.

I read in Maloberti's Data Converter text, that designing a single bit DAC, higher order (say order 5 as the example in Schreier Temes is) in something below 0.18um CMOS is not advisable to low signal swing at the opamps outputs which can cause stability issues for the converter.

Do you have any thoughts about this ? As mentioned the Schreier/Temes example is a 5 bit, single bit DAC Sigma Delta Design. I am using 0.13um CMOS process.

Would it be best for me to go for a higher level quantizer (multi bit DAC) if I am using a high order design ? I need to get 100 dB SNR, 14 bit resolution so I need a higher order to achieve that.

Thank you again for your understanding and patience, as I am new to these designs.

 

[erikl]

I read in Maloberti's Data Converter text, that designing a single bit DAC, higher order (say order 5 as the example in Schreier Temes is) in something below 0.18um CMOS is not advisable to low signal swing at the opamps outputs which can cause stability issues for the converter.

Do you have any thoughts about this ?

Signal swing depends on your supply voltage. I think you should use at least VDD=2.5V , better 3.3V .
Don't know if your process offers transistors for such supply voltage.

 

[ZoOneR]

Hi,
If you want more SNR, there are three ways: increase OSR, increase modulator order (I don't think you want that), increase the number of bits. If you choose to increase the number of bits, you must make sure that your DAC has sufficient linearity, because it's error directly affects the modulator. I'm sure you cand find out more informations in the book.

About the output swing... Usualy when someone wants to build a Delta Sigma Modulator(DMS) he starts with system level. This helps because you can go from the ideal DSM to a real one by inserting nonidealities one by one and see their effects. You can make a simulink model. In this way you can verify if you have your desired Noise Transfer Function (NTF) and Signal Transfer Function (STF). Also, you can check if the integrators have the wanted signal swing. If this doesn't happen, you do a coefficient scalling, and check again. After you are pleased with your system level design, you go on transistor level.

 

[Puppet123]

@erikl - I am using 0.13um CMOS - the supply voltage is 1.2V. Although I did see a paper, where they made a 4th order, discrete time sigma delta using 0.13um CMOS, with 0.9V supply voltage and low VT transistors. I attached that paper. But normally, I am not sure 1.2V will be enough for a 5th order, single bit Sigma Delta.

@zooner, yes, that is the design flow I am following - system level simulations in matlab/simulink then transistor design. My issue is the specs I have, I am supposed to make SNR of 100dB, with 14 bits. Even according to Schreier book, you need at least order 4 with multibit quantizer according to figures in his book, which I attached. So is it possible with low voltage supply as I asked @erikl, above ?

Thank you for your patience and understanding and time answering my questions.

 

[ZoOneR]

Hi,
What's your input signal bandwidth ?

 

[Puppet123]

SQNR > 100dB
14-bit (86dB SNDR)
1 MHz input bandwidth

 

[ZoOneR]

Hi,
I understand now why you want to increase the number of quantizier bits. I've made a DSM some time ago, but it was only second order, one bit quantizier. I know that for more bits you must use different algorithms to liniarize your DAC so your SNDR won't degrade.