mostly used verification language in industries?

[duheping]

For seperate module we use verilog, for the whole and large design we use vera.

 

[minhle]

I'm not sure about SystemC, but Tcl/tk is the most commonly used in backend design in industry

 

[bigyellow]

What's the main usage of Tcl/tk in backend?

 

[luoliuzhu]

I use vera now , but i will use systemverilog at next project .

 

[eruisi]

Script to control the behavior of EDA tools

What's the main usage of Tcl/tk in backend?

 

[beta0]

I usually use verilog+pli in my project.

 

[anilkumarv]

I think it is the system verilog that is being used more than SystemC.System verilog has more features when compared to others.

 

[xischaune]

I mostly use vera....
but system verilog with all its new powerful features is making me shift from vera to system verilog

 

[joelam]

i use vera now

 

[magic_andy]

I use verilog mostly

 

[nmurthy]

i use

verilog with scripting languages to verify the DUT(Design Under Test) with some PLI's so i feel verilog based verification is more popular than all and next comes system verilog due to its many advantages.

 

[alpeshchokshi]

recent trend is on C,VERILOG AND VERA
but the SYSTEM VERILOG is really going to be the next language for verification

 

[praveen_venigalla]

The use of verification language depends on the breadth of the project, available engineers and tools....

The languages like e,vera are already become porular as people are used to them.....

Now a days people are moving towards System verilog and System C, as many tools are suppoting these
languages. These languages are easily to adopt b'coz many poeple are familiar with C language and these languages are pretty similar when compared with C.

 

[hys]

VERA is set to phase out...
With the advent of System Verilog (SV), SYNOPSYS seems to be promoting SV more than VERA. So it is just a matter of time for VERA to be phased out.

Specman & e segment is still going great. But yes how much SV can impact this is not known... But if you ask people who are good with Specman, they dont see a need to move to SV for verification because everything they need is available in Specman. Further why to bother to learn another language (and become a newbie in it) when I am a master of "e".

At the same time assertion languages are also stepping in.... PSL, SVA etc... these are still in the infancy stages and not yet powerful enough to over turn the mights of Specman.

Best Regards,
Harish
https://hdlplanet.tripod.com/
https://groups.yahoo.com/group/hdlplanet