udir
Newbie level 5
Dear Friends
I am dealing with a board designed to output an RF signal at 1Mhz, 100V rms.
The circuit is an inverter that "builds" a square wave from a 24vdc , and then its filtered out to an approximate sine wave.
My problem is that the Mosfets that build this wave are after sometime gets really burnt out, and the heat sinks are changing color due to enormous heat that is probably inflicted on them m, despite the fan.
Ive made a few measurements with scope and the following came up:
1. When the circut is connected to a load, the Vdrain and I drain (lets say for Fet Q1) is quite reasonable and system is quiet.
2. When the circuit is NOT connected to a load, the Vdrain is fringing a lot and I see huge spikes of current (I figure about 50 amps momentarily)in the transitions between mosfet turn on and turn off.
My assumption is that the circuit is not designed to work with no load, but in fact it does and it causes me a lot of headaches.
Ive been trying to find a solution within current scope of design by adding fast recover diodes in parallel to the mosfets, add additional RC snubber between drains but it barley killed the large current spikes.
Any advise/proposal to improve the situation would be greatly appreciated.
If you will look at the schematics I added, some people advised me to place a common mode filter after the second stage to balance the 2 lines, but as far as i know this is mainly for EMC purposes and will not improve this situation.
also note that the capacitors that you see in parallel to each fet do not exist in the circuit.Attachment 99703 ()
Thanks a lot
Ron
I am dealing with a board designed to output an RF signal at 1Mhz, 100V rms.
The circuit is an inverter that "builds" a square wave from a 24vdc , and then its filtered out to an approximate sine wave.
My problem is that the Mosfets that build this wave are after sometime gets really burnt out, and the heat sinks are changing color due to enormous heat that is probably inflicted on them m, despite the fan.
Ive made a few measurements with scope and the following came up:
1. When the circut is connected to a load, the Vdrain and I drain (lets say for Fet Q1) is quite reasonable and system is quiet.
2. When the circuit is NOT connected to a load, the Vdrain is fringing a lot and I see huge spikes of current (I figure about 50 amps momentarily)in the transitions between mosfet turn on and turn off.
My assumption is that the circuit is not designed to work with no load, but in fact it does and it causes me a lot of headaches.
Ive been trying to find a solution within current scope of design by adding fast recover diodes in parallel to the mosfets, add additional RC snubber between drains but it barley killed the large current spikes.
Any advise/proposal to improve the situation would be greatly appreciated.
If you will look at the schematics I added, some people advised me to place a common mode filter after the second stage to balance the 2 lines, but as far as i know this is mainly for EMC purposes and will not improve this situation.
also note that the capacitors that you see in parallel to each fet do not exist in the circuit.Attachment 99703 ()
Thanks a lot
Ron
