As you have already said, only the top transistor is in saturation, the rest towards ground are in linear with the bottom one most strongly in linear. Your question is how to define Vgs and which Vgs to take into account. I will rephrase it as finding the overdrive voltage Vov, which is something you want to know if using that stacked transistors in analog design. I can offer you a kind of approximate answer to that. Today's transistors don't really behave like square low devices so exact formula will be difficult to come up with. Suppose you have one NMOS with W/L. You are mostly interested in the overdrive voltage Vov, which in square low speak is 2/(gm/Id), so actually for saturation you want to know gm/Id. Simplistically, for the same current and W/L, if transistor is in triode region its Ron=1/gm (gm being the gm when it is in saturation).
Now, if you put two of these transistors in series with the same gate voltage, the top one will be in saturation, the bottom one in triode. The Vov of the top NMOS is 2/(gm/Id) and the voltage drop across the bottom one is Ron*Id=1/(gm/Id). So, the "overdrive voltage" of the combined two transistor stack is 3/(gm/Id). If you have 3 transistors in series, you get something like 4/(gm/Id) and you can extrapolate further. You need to size the transistors such that the gm of the top one gives you the equivalent Vov that you need.
As I said, this is not exact. However, if you simulate the Id vs. the drain voltage of the top device (kind of the equivalent Vds of the stack) you can see that the equivalent transistor goes into saturation at about approximately (quite approximately but not terribly too much) that Vov.
If you want to share your simulation results here, it will be interesting to see what you get.