mosfet properties cadence

[AMSA84]

Hi guys,

I have doubt regarding the transistor properties in cadence. Please see the figure below:



Can you guys tell me the following:

- What is the W of the transistor?
- What is the m parameter there (in the picture)?

From what I know, when we have a transistor very large, we can cut him off in several small ones using the fingers. I don't know if I am thinking correctly, so that's why I am asking you to tell me the size of W to see if I am correct.

Regarads.

 

[dick_freebird]

The total W 1mm. That number is figured for you from
finger-width and number-of-fingers evidently. But the
"m" factor is not factored into this; instead I expect
it will just drive netlist instantiation of multiple devices
(for verification) and either a raw width multiplier or
a double instantiation in the Spectre netlist - you'd
have to pull that up, to see.

I would not call 100um a sensible finger width in this
technology node. It's liable to have very poor gate
resistance and source debiasing as well if laid out
end-fed.

 

[AMSA84]

Hi freebird and thanks for the quick reply.

But having a m = 2 doesn't mean that the total width will be 2000um?

This is something that I didn't knew and I was usted to work with the W and number of finger. In a book that I have they say that if we have a big transistor we can split him several gates (fingers) and then place them together. Thinking with m=1, I would say that I would instantiate a most with W=1000um with number of finger equal to 10. That would translate to 100um per finger times 10 equals 1000um.

Now, if I want a device with a width of 2000um, I should use a W=2000um and 20 fingers? With m=1, of I should user W=1000um with 10 fingers and m=2?

I have done a small test using the above mentioned parameters. When I use a multiplier of 2 the Layout XL generates two transistor with the same W, L and number of fingers.

I read in here: https://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.145.4198&rep=rep1&type=pdf (page 34) that "Describes the width of each MOSFET finger.
Total Device Width = Width * Number of finger * Multiplier", however it says at the same time that "“Number of Fingers” and “Multiplier” differ in simulation but are interpreted the same by this program. “Number of Fingers” implies merged sources/drains while “Multiplier” does not imply sharing. It is recommended that the user only change the “Number of Fingers” field so that layout and simulation will more closely match. "

I don't know if this is a reliable source, but I couldn't find any useful information on the web, even in Cadence website.

Just for the record: here: https://www.designers-guide.org/Forum/YaBB.pl?num=1351774957

This guy who says that when he uses the multiplier (in this case 16) the LVS gives him an error.

What I intend is to know which one of these parameters is better to use, multiplier or fingers for the better sizing of MOS?

I am confused!

freebird, could you elaborate this: "I would not call 100um a sensible finger width in this technology node. It's liable to have very poor gate resistance and source debiasing as well if laid out end-fed."?

Kind regards.

 

[dick_freebird]

The question is whether m= is represented by total
instance width, or by number of paralled instances,
in the various target netlists (LVS connectivity,
Spectre circuit), or not at all. You should inspect this
with some simple tests and make sure you're not
playing with a dummy property.

If you look at the gate geometry, your 100um gate
stripe at 340nm is about 300 squares of poly resistor
(divided by 10 parallel). This will make a distributed
RC network of some consequence, against the Cgd
Miller capacitance, affecting high frequency and high
edge rate signals. A proper RF or high speed digital
driver would probably prefer 100 fingers of 10um,
over 10@100um (about a decade's worth of
ultimate bandwidth).

If you feed the source from one end of the stripe,
you can expect maybe 100-200 squares of
longitudinal resistance and if (say) Rs=0.1 ohms
for aluminum-strapped silicided N+ active you would
have something like 10-20 ohms/finger and at 1mA
per finger, maybe 20mV of end-end debiasing. This
will crowd current to one end and make the evident
W "fall away" at higher currents. Layout style can
address this, for the most part, if you're concerned.

 

[erikl]

This guy who says that when he uses the multiplier (in this case 16) the LVS gives him an error.

In this case (multiplier m>1) you should use a device array in schematics, e.g. MOS0<1:16>.

(I prefer the nomenclature <1:16> for arrays, to differentiate from a bus nomenclature, which would be called <15:0> ).

 

[AMSA84]

Hi freebird and thanks again for the reply and to erikl.

Regarding the question of the sensible finger width, in my case this is to design a power mosfet. I think that this issue that you referred doesn't apply here? At least for simulating. I tried a small experience with a transistor using m=1 (W=2mm, 20 fingers - 100um/finger) and m=2 (W=1mm, 10 fingers -100um/finger) and the results were the same. Basically.

This issue is more related to the layout, right? When we are in designing the layout, right?

The question is whether m= is represented by total
instance width, or by number of paralled instances,
in the various target netlists (LVS connectivity,
Spectre circuit), or not at all. You should inspect this
with some simple tests and make sure you're not
playing with a dummy property.

If you look at the gate geometry, your 100um gate
stripe at 340nm is about 300 squares of poly resistor
(divided by 10 parallel). This will make a distributed
RC network of some consequence, against the Cgd
Miller capacitance, affecting high frequency and high
edge rate signals. A proper RF or high speed digital
driver would probably prefer 100 fingers of 10um,
over 10@100um (about a decade's worth of
ultimate bandwidth).

If you feed the source from one end of the stripe,
you can expect maybe 100-200 squares of
longitudinal resistance and if (say) Rs=0.1 ohms
for aluminum-strapped silicided N+ active you would
have something like 10-20 ohms/finger and at 1mA
per finger, maybe 20mV of end-end debiasing. This
will crowd current to one end and make the evident
W "fall away" at higher currents. Layout style can
address this, for the most part, if you're concerned.

 

[dick_freebird]

The issue for power devices is that longitudinal source
stripe resistance is not represented. So in simulation it
doesn't matter how you specify the device, and you
get no coaching from it.

Depending on the technology a 100um finger width may
also put you afoul of "well tap" rules that assert a maximum
distance from active to tap (I've seen 20um rules). A very
large untapped well, is a weakly-shunted base of a
parasitic lateral BJT and unmodeled breakdown / leakage
action may be a risk.