I need some imformation about the mismatch of the mosfet transistors, especially about this phenomenon in the differencial pairs. I was seeking this topic but I haven't found any information.
I really need that.
In my opinion
first, you can use symmetry structure which you can find in many books.
second, you can refer to the foundry which you can get their PCM or electronics parameter, and maybe here are some discreption about mismatch parameter. You can calculate the MOS by the mismatch parameter.
third, you could know the circuit's precision.
There are two ways to reduce the offset.
1. through design. choose device with large width. output stage should be banlance to remove the systematic offset. current source's length should be maximized.
2. Through layout, using centroid and interdigitization
Read Alan Hasting's "The Art of Analog Layout", Chapter 7 is named Matching of Resistors and Capacitors but inside it mention matching techniques applicable to every component, in particular you'll find good explanations and examples of Interdigitation and CommonCentroid.