Are you designing an IC? If so, the k value as well as many other parameters will be in the process specifications. If you are not designing an IC, what are you designing and what transistors are you looking at?
I am currently using an nMOS and a pMOS - SI2302ADS and NTR1P02LT1G to switch some switch low power to external peipherals. On the nMOS I am connecting load from vdd to the drain and on the pMOS load from vdd to the source.
On the PMOS I am trying to figure out the expected Id based on the saturation equation of Id = kn(vgs - vt)^2. The Id measured is not what expected and there is a higher than expected voltage on Vds. So I am having to go to the equations to see if things match up and if they do what I am doing wrong. In the college days we would simply guess what region of operation the FET is in and use the appropriate Id equation to figure out current - voltages in the circuit and see if the region was correct. Of course the kn values were always given in the text problems.
So I am wondering how current - voltage analysis in the circuit is done in practice for MOSFETs of similar configurations?