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Mos switch can be over several tens of um?????

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ljy4468

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Hi
everyone!
I've question about mos switch size.
Can be switch size over 70um, 100um(gate) without using multiplier or finger?
Of course There are no problem in simulation If I use big size switch
But I think there are problem in layout
I heard that multiplier or finger structure is recommended for gate over 20um.
Which is true?

thanks in advance.
 

eda_freak

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Hi!!
i think that by switch u mean the width of the MOS device...yes actually u can simulate for larger widths of device but you should break it down into multiples i.e. fingers...this ideally should also be reflected in your spice netlist by multiples(M value) for the device simulation..... larger widths have larger gate and diffusion capacitances associated with them... so its always smart way to break em down into smallerer managable fingers....now this also helps in making good layouts especially when u are making digital cell libraries...which have size specifications(technology definations).
 

venkateshr

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It is highly advisable to use fingers if u want to emulate a high width mosfet.the reasons are

1. Capacitances(diffusion) will be heavily reduced due to sharing of drains

2.gate resisntace will be heavil reduced and this aids the freq. response .

3. layout is easy (when space is concerned)
 

paulux

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Is there any optimum way to split this multiple finger? Any criteria, consideration from real example? Thanks for comments
 

jutek

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hello

when i divide large (10m) PMOS into 1000 fingers, nothing changes. Capacities are still the same.

should i split it into 10 fingers and connect 100 transistor parallelly to see the result?

it also doesn't change antyhing. i use tsmc 0.18um

regards
 

rockycheng

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jutek,

You are right. Cgs and Cgd are not affected, when you devide the long gate into many fingers, since the total transistor width remains the same. However, when the finger number is large enough, the drain and source capacitances shall become almost half.
 

Milad-D

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An example to see the effect of Rgate on the clock signal rise/fall time for high speed operation.

The sheet resistance of poly-silicon is about 20ohms/square. Let say L=0.06um and W=100um then the gate resistance will be 233 ohms ( effectively divided by 2, due to distributed nature of it)and the Cgs is about 100fF. Therefore the RC is equal to 11.65 pS. If you drive the switches with high speed clocks, let say 30 ps rise/fall time and ideal inverters, then you have degradation in clock shape.

But if you use, let say 20 fingers, then Rgate will be reduced to 233/(20*20) ( effectively half of it) and therefore the RC of the MOS is 28.75fS which is very good.
 

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