ranaya
Advanced Member level 4

Hi all,
I've got a question about the MOS transistor length range in HCMOS 9GP 130 nm technology. I've implemented a current mirror circuit for SAR ADC with high speed transistors. The problem I have at the moment is I cannot increase the high speed transistor length beyond 0.4u in cadence simulation. Here simulation in the sense, I cannot directly apply that larger L value to the transistor properties. But in specter, the dc sweep of currents over length of transistor is possible for larger length values (>0.4u). According to both model file and design rule manual, the Lmax is set to 0.4u.
But in order to obtain 0.5 LSB accuracy in current mismatch, at least the L should be increased to 3u (have tried many current mirror topologies). So if the model does not accept that value, does it mean that the above mentioned technology cannot process a transistor with larger L values (let's say 3u) ? Or is it only for the sake of simulation ? Any explanation will be appreciated !
Thank You
I've got a question about the MOS transistor length range in HCMOS 9GP 130 nm technology. I've implemented a current mirror circuit for SAR ADC with high speed transistors. The problem I have at the moment is I cannot increase the high speed transistor length beyond 0.4u in cadence simulation. Here simulation in the sense, I cannot directly apply that larger L value to the transistor properties. But in specter, the dc sweep of currents over length of transistor is possible for larger length values (>0.4u). According to both model file and design rule manual, the Lmax is set to 0.4u.
But in order to obtain 0.5 LSB accuracy in current mismatch, at least the L should be increased to 3u (have tried many current mirror topologies). So if the model does not accept that value, does it mean that the above mentioned technology cannot process a transistor with larger L values (let's say 3u) ? Or is it only for the sake of simulation ? Any explanation will be appreciated !
Thank You