Monte Carlo Analysis - Process gradients on a chip

[mvj]

Hi All,

When we run MonteCarlo Analysis for variations in the process ("Process only"), does it also consider process gradients across the die area or does it work some other way.for example, does it simulate the variations in resistace of a resistor if it were placed at the right end of a chip compared to the same resistor being placed at the left end of the chip.


Thanks,
M.

 

[pavel_adameyko]

Hello
I suppose the answer is no. "Process only" implies only variations on corners.
Regards.

 

[dgnani]

Hi All,

When we run MonteCarlo Analysis for variations in the process ("Process only"), does it also consider process gradients across the die area or does it work some other way.for example, does it simulate the variations in resistace of a resistor if it were placed at the right end of a chip compared to the same resistor being placed at the left end of the chip.


Thanks,
M.

process only simulates statistical variations within corners, there will be no mismatch between devices; mismatch can either use on-chip-variations or mismatch between closely related devices, it really depends on the PDK...

 

[mvj]

it really depends on the PDK...

May I know what you ment by PDK..??

Thank you,
M.

 

[dgnani]

PDK stands for Process Design Kit

 

[jimito13]

PDK means Process Design Kit,in other words it's the process/technology you work with.

 

[dick_freebird]

Gradient would require you to assign location to every
device and have a "surface map" or at least some
description of the cross-chip systematic variation.
I have never seen this and I doubt you have the
structure, let alone the data to populate it.

Furthermore the die-scale gradient is likely smaller
than random variation and local layout / litho effects,
especially when the die is small relative to wafer dia
on a mature process.

 

[mvj]

Gradient would require you to assign location to every
device and have a "surface map" or at least some
description of the cross-chip systematic variation.
I have never seen this and I doubt you have the
structure, let alone the data to populate it.

How about doing the layout of two devices by keeping them apart at a distance that I am interested in and then running Monte Carlo analysis of the extracted layout?

The problem is that I need to do the layout of a string of resistors as part of a resistive DAC and wanted to know if I would be required to split each resistor into two and use layout methods similar to common centroid method (to over come process gradients) which is becoming very complex to do the connections.

Any suggestions in this regard are more than welcome..

Thanks,
M.

 

[Teddy]

As said above - Monte Carlo process is running statistical variation (gauss) within /- 3 sigma arround typical process. In this case all devices have the same model for each run. Each run will consider different model within the gaussian distribution. That said you with your resistors will see variation over process and how sensitive your design is for process variation only.
What you are asking about is more to run Monte Carlo mismatch analysis where (if run correctly) each resistor segment would get different size which is defined by gaussian (usualy +/-1sigma or more) distribution around its typical (schematic) values. This models physical variations in processing.
Or if you are interested for die-die variation you can run yield analysis.
But none of those will give you definite answer.
In any case (unles your DAC design is insensitive to resistor variations) it is good idea to spend more time on layout... than regret later on.

 

[dick_freebird]

If you do believe there's a gradient and you can quantify
it (say, based on PCM data and an idea of the site separation)
there's nothing stopping you going at it old school. Parameterize
each leg with (say) 10K+drdx*2u, 10K+drdx*4u, ... based on
your layout particulars, and see what the outcome is. There
is a whole lot in this world that canned tools won't help you
with.

If you had raw WAT data from widely spaced sites you could
arrive at a rough idea of worst case gradient. Bearing in mind
that a plain gradient is not the norm and crescent or annular
shapes can be common.

If you laid out a resistor bank & made a schematic with an
explicit gradient and played only with rewiring, that might
show you a best arrangement. But be sure and check what
happens in the reverse slope case.
then

 

[lovexxnu]

This depends on the resolution of your DAC and the variation of the resistor. you can find in the fab's document. if you don't use the central symmetric, add some dummy at least.

How about doing the layout of two devices by keeping them apart at a distance that I am interested in and then running Monte Carlo analysis of the extracted layout?

The problem is that I need to do the layout of a string of resistors as part of a resistive DAC and wanted to know if I would be required to split each resistor into two and use layout methods similar to common centroid method (to over come process gradients) which is becoming very complex to do the connections.

Any suggestions in this regard are more than welcome..

Thanks,
M.