module definition of D flip-flop

[funjoke]

d flip flop

module dff
(output reg op_q,
output op_q_n,
input ip_data,
input ip_aset_n,
input ip_areset_n,
input ip_clock);

Write a behavioural description of the D flip flop(DFF) that fulfils the following specification
-The DFF is synchronised to the rising edge of a clock
-The DFF has an active-low asynchoronous reset
-The DFF has an active-low asynchoronous set
-The reset has priority over the set



The answer is :
always@(posedge ip_clock)
if(!ip_areset_n)
op_q<=0;
else
op_q<=ip_data;



i dunno know how to do it le ,can anybody help ?

 

[mytechface]

always@(posedge ip_clock or negedge ip_aset_n or ip_areset_n )
if(!ip_areset_n)
op_q<=0;
else if(!ip_set_n)
op_q<=1;
else
op_q<=ip_data;

 

[funjoke]

this is the only answer ?but i haven finish do it