modelsim simulation formate

[vivo_m]

hello everybody,

i'm trying to simulate my vhdl file using modelsim but actually it is taking the input value in hex format..
i.e at the wave window, when i right click my input port and choose force, "32'hXXXXXXXX" is wrote in the value field..
i don't know what to do to make it "uuuuu..." and accept binary value..

any idea how can i overcome this plzzzz

beside that i'm getting this warning when start simulation
"
# Loading work.testing_sim(behavioral)
# ** Warning: Design size of 18505 statements or 1 leaf instances exceeds ModelSim PE Student Edition recommended capacity.
# Expect performance to be quite adversely affected.
"

after forcing the input signals to its proper value.. i got this warning
"
# ** Failure: ARG is too large in CONV_INTEGER
# Time: 100 ns Iteration: 0 Process: /testing_sim/line__49 File: E:/vhdl_Code/testing_sim.vhd
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 100 ns Iteration: 0 Instance: /testing_sim
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
# Time: 100 ns Iteration: 0 Instance: /testing_sim
"
and simulation stops at a line that i'm dividing 2 variables, each of size (32*2) std_logic_vector, i'm converting them into integer value using conv_integer() function to apply division operation

i tried to make them 32 only but i got this error
"
# ** Fatal: (vsim-3977) Integer divide by zero.
# Time: 100 ns Iteration: 0 Process: /testing_sim/line__49 File: E:/vhdl_Code/testing_sim.vhd
# Fatal error in Process line__49 at E:/vhdl_Code/testing_sim.vhd line 86
#
"
although i'ven't set any of the values to zero..

i'm using Modelsim PE 10.2


any help plzzzz.....


thanks...

 

[yourcheers]

you can do the force from modelsim command prompt. try that.

 

[vivo_m]

yes i did so as "32b'......"
but when using vsimulink and dealing with matlab this doesn't work as its taking input from matlab as binary values and reads it in modelsim as hex leading to overflow and unexpected output..

is there a problem with my modelsim version or this is the default of this new version as i've just downloaded it 2 days ago and the previous one i was working on was taking input normaly in binary format...

any idea plzzz..

thanks alot..

 

[sureshaa]

Dude,

Can you post your code also?

 

[vivo_m]

guys i made some work arround and it succeeded

for the data format acceptance to be binary by default
simulate -> runtime options -> then selected binary to be default radix..

for dividing by zero
i added if condition to ensure that the denum not equal zero but this dosen't work
so i built a component to be used for division and so it goes

but for this lazy warning
"
# Loading work.testing_sim(behavioral)
# ** Warning: Design size of 18505 statements or 1 leaf instances exceeds ModelSim PE Student Edition recommended capacity.
# Expect performance to be quite adversely affected.
"
nothing changed except that the # of statements and # of leaf instances increased to 've a warning like that
"
# Loading work.testing_sim(behavioral)
# ** Warning: Design size of 22405 statements or 12 leaf instances exceeds ModelSim PE Student Edition recommended capacity.
# Expect performance to be quite adversely affected.
"

any idea plzzz..

thanks alot

 

[ads_ee]

There is a limit to how big a design the PE student edition will support and run at its full potential. Once your design gets too big well it will slow down.

Only fix would be to either a) optimized the design so it is smaller or b) do sub module simulations only.