Hi to all,
I wonder if it is possible to simulate a synthesised netlist by design compiler in modelsim.
I'm finding that after the synthesis of design vision the output is a file with some component of my library instanciated, for example this:
Code:
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
then instanciated into my architetture body
Code:
U7 : XOR2_X1 port map( A => n1, B => n6, Z => next_state_2_port)
I like to import this vhdl file into modelsim, add some file of my library containing the definition of that components and simulate the netlist. I googled a lot but i cannot manage to find the proper solution.
where can i find my library components in order to link properly to the modelsim in order to find the require components? or can anyone give me some advice to solve my problem?
thanks in advice
You sure can. There should be a verilog file that comes with your std cell library, in there all gates are logically defined, and some models include a rough timing estimation too.
Thank you for your reply.
In my library folder i have 1 file .lib and 1 .db.
I tried to import them in modelsim but it doesn't recognize as library. Where can i find that verilog file to link in modelsim? are any method to import .lib file into modelsim?