modelsim SE 6.4 having problem with mailbox in system verilog.

[bntpathak]

we are creating a driver, transactor, generator, program, interface, DUT file and a top. In top file when load all given files then this type of error produce.
# Loading work.test
# ** Error: (vsim-3978) generator.sv(16): Cannot assign an unpacked type to a packed type.
# Time: 0 ns Iteration: 0 Region: /top/tst File: E:/lab2 sram/program.sv
# Error loading design



code of generator
typedef class packet;
class generator;
packet pkt;
// parameter type T = bit;
mailbox mbx;

function new(mailbox mbx);
this.mbx = mbx;//(100);
endfunction


task run(int count);
repeat (count) begin
pkt = new();
void'(pkt.randomize);
mbx.put(pkt);
end
endtask

endclass

please help me to ignore this error.

 

[dave_59]

Early versions of modelsim do not support untyped mailboxes.

My recommendation is to always use typed mailboxes anyways - it is safer.


class generator;
packet pkt;
// parameter type T = bit;
mailbox #(packet) mbx;

function new(mailbox#(packet) mbx);
this.mbx = mbx;//(100);
endfunction


task run(int count);
repeat (count) begin
pkt = new();
void'(pkt.randomize);
mbx.put(pkt);
end
endtask

endclass