[SOLVED] modelsim: Illegal output or inout port connection

Status
Not open for further replies.
R

ramanandn

Newbie level 6
Joined
Oct 1, 2010
Messages
12
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,283
Activity points
1,373
Hi guys,

I have an output port (reg) in a module. That module is instantiated in my top level module, with that output signal as wire to a pin on the CPLD.

I don't assign anything to this in my tb (since it would be an input into the tb).

But I still get the above error from Modelsim. The compilation goes through fine which makes me think that my tb has an issue. But I do nothing with this signal in my tb.

Any thoughts?
 

The top level pin must be either in- or output. If it's input, you get an error.
 

Sorry I didn't understand. The top level pin cannot be input??!
 

Right, a pin wired to an output of a lower level entity or a register at the top level entity can't be of the input type.
 

I understand that.. it is still output out of the top level. It is input to the testbench. I don't use it in the tb.
 

According to your description, there should be no error.
 

I have an output port (reg) in a module.
I don't assign anything to this in my tb (since it would be an input into the tb).
Click to expand...

you are using a reg instead of a wire in your testbench, that's the only way to get this error.

Alex
 

i didnot quite follow what you said,maybe you can shou some code of your design.

just note that:in testbench,there should be only reg or wire,that is,if a signal in your design project is declared as input,then in your testbench,you should define it as reg;otherwise,define it wire.No tri-state in testbench!

hope it helps
 
Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…